MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 1190

MPU POWERQUICC III 783-PBGA

MPC8544VTALF

Manufacturer Part Number
MPC8544VTALF
Description
MPU POWERQUICC III 783-PBGA
Manufacturer
Freescale Semiconductor
Datasheets

Specifications of MPC8544VTALF

Processor Type
MPC85xx PowerQUICC III 32-Bit
Speed
667MHz
Voltage
1V
Mounting Type
Surface Mount
Package / Case
783-FCPBGA
Processor Series
MPC85xx
Core
e500
Data Bus Width
32 bit
Maximum Clock Frequency
667 MHz
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Data Ram Size
32 KB
I/o Voltage
1.8 V, 3.3 V
Interface Type
I2C, HSSI, DUART
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

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Part Number
Manufacturer
Quantity
Price
Part Number:
MPC8544VTALF
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MPC8544VTALFA
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Global Utilities
19.4.1.24 SerDes 1 Control Register 1 (SRDS1CR1)
Shown in
of the SerDes 1 signals. Note that reserved fields with non-zero reset values are for internal use only and
their values should be preserved.
Table 19-27
19-24
Offset 0xE_0F04
Reset 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0
W
16–19
20–23
24–31
R
0–15
Bits
0
Figure
describes the bit settings of SRDS1CR1.
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
XMITEQAD
XMITEQEH
19-24, SRDS1CR1 contains the control bits used for adjusting the transmit equalization
Name
Figure 19-24. SerDes 1 Control Register 1 (SRDS1CR1)
Reserved
Transmit equalization selection bus for SerDes 1 lanes a–d (SD1_RX/TX[0:3])
Default value = 4’b0100
MSB (bit 16) is amplitude select:
0 = Vdd-diff-pk=pk
1 = 5/6 Vdd-diff-pk=pk
LSBs (bits 17:19) are equalization amplitude:
000 No equalization
001 1.09x relative amplitude
010 1.2x relative amplitude
011 1.33x relative amplitude
100 1.5x relative amplitude
101 1.71x relative amplitude
110 2.0x relative amplitude
111 reserved
Transmit equalization selection bus for SerDes 1 lanes e–h (SD1_RX/TX[4:7])
Default value = 4’b0100
MSB (bit 20) is amplitude select:
0 = Vdd-diff-pk=pk
1 = 5/6 Vdd-diff-pk=pk
LSBs (bits 21:23) are equalization amplitude:
000 No equalization
001 1.09x relative amplitude
010 1.2x relative amplitude
011 1.33x relative amplitude
100 1.5x relative amplitude
101 1.71x relative amplitude
110 2.0x relative amplitude
111 reserved
Reserved
Table 19-27. SRDS1CR1 Field Descriptions
15 16
0
XMITEQAD
1
0
Description
19 20
0
0
XMITEQEH
1
0
23 24
0
0
0
Freescale Semiconductor
0
Access: Read/Write
1
1
0
0
31
0

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