MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 1052

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PCI Bus Interface
The POR reset values for the affected configuration bits are described in
17.5.1.1
When the device powers up in host mode, all inbound configuration accesses are ignored (and thus master
aborted). The PBFR[ACL] bit is a don’t care. The device powers up with the ability to master transactions
on the PCI bus, however in order to acknowledge memory transactions, the memory space bit must be set.
17.5.1.2
When the device powers up in agent mode, it acknowledges inbound configuration accesses. However the
device cannot master transactions or acknowledge inbound memory accesses on the PCI bus until the
appropriate configuration bits (bus master and memory space, respectively) have been set.
17.5.1.3
Agent configuration lock mode is similar to agent mode with the added restriction that when the device
powers up in agent configuration lock mode, it retries all inbound configuration accesses until the
PBFR[ACL] bit is cleared. The purpose of this mode is to allow initial configuration on the port by the
local processor before opening the port to be further configured by the external host. As in agent mode,
the device in agent configuration lock mode cannot master transactions or acknowledge inbound memory
accesses on the PCI bus until the appropriate configuration bits (bus master and memory space,
respectively) have been set.
17-68
PCI Bus Function
Register (offset) Bit
Register
(0x44)
Host Mode
Agent Mode
Agent Configuration Lock Mode
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Table 17-53. Affected Configuration Register Bits for POR (continued)
5
0
Table 17-54. Power-On Reset Values for Affected Configuration Bits
Host
Agent
Agent configuration lock
Name
ACL
PAH
Valid only in agent mode. Controls acknowledgement of inbound configuration accesses.
If set, all inbound configuration accesses are retried. If cleared, inbound configuration
accesses are acknowledged.
In host mode all inbound configuration accesses end in master aborts.
Determines whether the device is in agent or host mode. Zero indicates host mode.
Mode
Master
Bus
1
0
0
Memory
Space
Configuration Bit
Register Description
0
0
0
ACL
X
0
1
Table
PAH
0
1
1
17-54.
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