MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 964

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

DMA Controller
16.3.1.11
The next list descriptor address registers, shown in
the next list descriptor in memory. If the contents are transferred to the current list descriptor address
register they become effective for the current transfer in extended chaining mode.
Table 16-17
16.3.1.12
The source stride register, shown in
stride information is loaded when a new list descriptor is read from memory. Therefore, the source stride
register is applicable for all link descriptors in the new list. Changing the source stride information for a
link requires that a new list be generated.
16-22
Offset 0x13C
Reset
Offset 0x138
Reset
27–30
W
R
W
0–26
Bits
R
31
0x1BC
0x23C
0x2BC
0
0x1B8
0x238
0x2B8
0
EOLSD End-of-lists descriptor. This bit is ignored in direct mode.
NLSDA Next list descriptor address. Contains the low-order bits of the 36-bit next descriptor address of the
Name
describes the fields of the NLSDARn.
(NLSDAR n and ENLSDAR n )
—
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Next List Descriptor Address Registers
Source Stride Registers (SSR n )
Figure 16-18. Extended Next List Descriptor Address Registers (ENLSDAR n )
buffer descriptor in memory. The descriptor must be aligned on a 32-byte boundary.
Reserved
0 This list descriptor is not the last list descriptor in memory.
1 This list descriptor is the last list descriptor in memory. If this bit is set, then the DMA controller
Figure 16-19. Next List Descriptor Address Registers (NLSDAR n )
halts after the last link descriptor transaction is finished.
Table 16-17. NLSDAR n Field Descriptions
Figure
NLSDA
16-20, contains the stride size and distance. Note that the source
—
Figure 16-18
All zeros
All zeros
Description
and
Figure
16-19, contain the address for
26
27
Freescale Semiconductor
Access: Read/Write
—
27 28
Access: Mixed
30
ENLSDA
EOLSD
31
31