MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 35
![MPU POWERQUICC III 783-PBGA](/photos/37/62/376266/mpc8544e_image_sml.jpg)
MPC8544VTALF
Manufacturer Part Number
MPC8544VTALF
Description
MPU POWERQUICC III 783-PBGA
Manufacturer
Freescale Semiconductor
Datasheets
1.MPC8544VTALF.pdf
(117 pages)
2.MPC8544VTALF.pdf
(2 pages)
3.MPC8544VTALF.pdf
(1340 pages)
Specifications of MPC8544VTALF
Processor Type
MPC85xx PowerQUICC III 32-Bit
Speed
667MHz
Voltage
1V
Mounting Type
Surface Mount
Package / Case
783-FCPBGA
Processor Series
MPC85xx
Core
e500
Data Bus Width
32 bit
Maximum Clock Frequency
667 MHz
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Data Ram Size
32 KB
I/o Voltage
1.8 V, 3.3 V
Interface Type
I2C, HSSI, DUART
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC8544VTALF
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MPC8544VTALFA
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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- Download datasheet (12Mb)
Paragraph
Number
17.3.1.4.2
17.3.1.4.3
17.3.1.4.4
17.3.1.4.5
17.3.1.4.6
17.3.1.4.7
17.3.1.4.8
17.3.1.4.9
17.3.2
17.3.2.1
17.3.2.2
17.3.2.3
17.3.2.4
17.3.2.5
17.3.2.6
17.3.2.7
17.3.2.8
17.3.2.9
17.3.2.10
17.3.2.11
17.3.2.12
17.3.2.13
17.3.2.14
17.3.2.15
17.3.2.16
17.3.2.17
17.3.2.18
17.3.2.19
17.3.2.20
17.4
17.4.1
17.4.1.1
17.4.1.2
17.4.1.3
17.4.1.4
17.4.2
17.4.2.1
17.4.2.2
17.4.2.3
17.4.2.3.1
Freescale Semiconductor
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Functional Description................................................................................................. 17-42
PCI Configuration Header ....................................................................................... 17-30
PCI Bus Arbitration ................................................................................................. 17-42
PCI Bus Protocol ..................................................................................................... 17-45
PCI Vendor ID Register—Offset 0x00 ................................................................ 17-30
PCI Device ID Register—Offset 0x02 ................................................................ 17-31
PCI Bus Command Register—Offset 0x04 ......................................................... 17-31
PCI Bus Status Register—Offset 0x06................................................................ 17-32
PCI Revision ID Register—Offset 0x08 ............................................................. 17-34
PCI Bus Programming Interface Register—Offset 0x09 .................................... 17-34
PCI Subclass Code Register—Offset 0x0A......................................................... 17-35
PCI Bus Base Class Code Register—Offset 0x0B .............................................. 17-35
PCI Bus Cache Line Size Register—Offset 0x0C............................................... 17-35
PCI Bus Latency Timer Register—0x0D ............................................................ 17-36
PCI Base Address Registers ................................................................................ 17-36
PCI Subsystem Vendor ID Register..................................................................... 17-38
PCI Subsystem ID Register ................................................................................. 17-39
PCI Bus Interrupt Line Register .......................................................................... 17-39
PCI Bus Interrupt Pin Register ............................................................................ 17-40
PCI Bus Minimum Grant Register (MIN_GNT)................................................. 17-40
PCI Bus Maximum Latency Register (MAX_LAT)............................................ 17-41
PCI Bus Function Register (PBFR) ..................................................................... 17-41
PCI Bus Arbiter Configuration Register (PBACR)............................................. 17-42
PCI Bus Arbiter Operation .................................................................................. 17-43
PCI Bus Parking .................................................................................................. 17-44
Broken Master Lock-Out ..................................................................................... 17-45
Power-Saving Modes and the PCI Arbiter .......................................................... 17-45
Basic Transfer Control......................................................................................... 17-45
PCI Bus Commands............................................................................................. 17-46
Addressing ........................................................................................................... 17-47
PCI Bus Capabilities Pointer Register ................................................................. 17-39
PCI Error Capture Disable Register (ERR_CAP_DR).................................... 17-25
PCI Error Enable Register (ERR_EN) ............................................................ 17-26
PCI Error Attributes Capture Register (ERR_ATTRIB) ................................. 17-27
PCI Error Address Capture Register (ERR_ADDR)....................................... 17-28
PCI Error Extended Address Capture Register
PCI Error Data Low Capture Register (ERR_DL) .......................................... 17-29
PCI Error Data High Capture Register (ERR_DH)......................................... 17-29
PCI Gasket Timer Register (GAS_TIMR) ...................................................... 17-29
Memory Space Addressing.............................................................................. 17-47
(ERR_EXT_ADDR).................................................................................... 17-28
Contents
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Number
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