MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 440

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Programmable Interrupt Controller
10.3.7.4
Internal interrupt destination registers (IIDRs), shown in
EIVDRs, except that they apply to the internal interrupt sources listed in
interrupts, internal interrupts can be directed only to processor 0.
Table 10-43
10-42
12–15 PRIORITY Priority. Specifies the interrupt priority. The lowest priority is 0 and the highest priority is 15. A priority level
16–31 VECTOR Vector. The vector value in this field is returned when the interrupt acknowledge (IACK) register is read and
Offset IIDR0–7 0x5_0210, 0x5_0230, 0x5_0250, 0x5_0270, 0x5_0290, 0x5_02B0, 0x5_02D0, 0x5_02F0
Reset 0
Bits Name
9–11
Bits
0
1
8
W
R
IIDR8–15
IIDR16–23
IIDR24–31
IIDR32–39
IIDR40–47
EP CI
EP
CI
0
Name
—
P
1
0
External pin. Allows internal interrupt to be serviced externally.
0 Internal interrupt is serviced internally with int signal to the processor core.
1 Internal interrupt is directed to IRQ_OUT for external service. The behavior of the PIC is not defined if both EP
Critical interrupt.
0 Internal interrupt is serviced internally with int signal to the processor core.
1 Internal interrupt is directed to the processor 0 as a critical interrupt with the cint signal. The behavior of the PIC
describes the IIDR fields.
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
and CI are set on the same interrupt destination register.
is not defined if both EP and CI are set on the same interrupt destination register.
Internal Interrupt Destination Registers (IIDR0–IIDR47)
The behavior of the PIC unit is not defined if both the EP and CI bits of the
same interrupt destination register are set.
2
0
Polarity. Specifies the polarity for the internal interrupt. Note: Because all internal interrupts are active-high,
clearing this bit disables the interrupt.
0 Interrupt polarity is active-low. This value disables the interrupt.
1 Interrupt polarity is active-high. This is the reset value and should not be changed.
Reserved.
of 0 disables interrupts from this source.
this interrupt resides in the interrupt request register (IRR) shown in
0x5_0310, 0x5_0330, 0x5_0350, 0x5_0370, 0x5_0390, 0x5_03B0, 0x5_03D0, 0x5_03F0
0x5_0410, 0x5_0430, 0x5_0450, 0x5_0470, 0x5_0490, 0x5_04B0, 0x5_04D0, 0x5_04F0
0x5_0510, 0x5_0530, 0x5_0550, 0x5_0570, 0x5_0590, 0x5_05B0, 0x5_05D0, 0x5_05F0
0x5_0610, 0x5_0630, 0x5_0650, 0x5_0670, 0x5_0690, 0x5_06B0, 0x5_06D0, 0x5_06F0
0x5_0710, 0x5_0730, 0x5_0750, 0x5_0770, 0x5_0590, 0x5_07B0, 0x5_07D0, 0x5_07F0
0
0
Figure 10-39. Internal Interrupt Destination Registers (IIDRs)
0
Table 10-42. IIVPR n Field Descriptions (continued)
0
0
Table 10-43. IIDR n Field Descriptions
0
0
0
0
0
NOTE
0
Description
0
Description
Figure
—
0
0
0
10-39, have the same fields and format as
0
0 0 0 0 0 0 0 0 0 0 0 0
Figure
Table
10-48.
10-43. Like external
Freescale Semiconductor
Access: Mixed
30 31
P0
1