MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 54

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Figure
Number
14-13
14-14
14-15
14-16
14-17
14-18
14-19
14-20
14-21
14-22
14-23
14-24
14-25
14-26
14-27
14-28
14-29
14-30
14-31
14-32
14-33
14-34
14-35
14-36
14-37
14-38
14-39
14-40
14-41
14-42
14-43
14-44
14-45
14-46
14-47
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Transfer Error Status Register (LTESR) ............................................................................. 14-24
Transfer Error Check Disable Register (LTEDR) ............................................................... 14-25
Transfer Error Interrupt Enable Register (LTEIR).............................................................. 14-26
Transfer Error Attributes Register (LTEATR) .................................................................... 14-27
Transfer Error Address Register (LTEAR) ......................................................................... 14-29
Local Bus Configuration Register....................................................................................... 14-29
Clock Ratio Register (LCRR) ............................................................................................. 14-30
Basic Operation of Memory Controllers in the LBC.......................................................... 14-32
Example of 8-Bit GPCM Writing 32 Bytes to Address 0x5420 ......................................... 14-34
Basic LBC Bus Cycle with LALE, TA, and LCSn ............................................................. 14-35
Local Bus to GPCM Device Interface ................................................................................ 14-37
GPCM Basic Read Timing (XACS = 0, ACS = 1x, TRLX = 0) ........................................ 14-37
GPCM Basic Write Timing (XACS = 0, ACS = 00, CSNT = 1, SCY = 1,
GPCM Relaxed Timing Read (XACS = 0, ACS = 1x, SCY = 1,
GPCM Relaxed Timing Back-to-Back Writes (XACS = 0, ACS = 1x, SCY = 0,
GPCM Relaxed Timing Write
GPCM Relaxed Timing Write
GPCM Read Followed by Read (TRLX = 0, EHTR = 0, Fastest Timing) ......................... 14-44
GPCM Read Followed by Write (TRLX = 0, EHTR = 1,
GPCM Read Followed by Write
External Termination of GPCM Access.............................................................................. 14-46
Connection to a 32-Bit SDRAM with 12 Address Lines.................................................... 14-48
SDRAM Address Multiplexing .......................................................................................... 14-51
PRETOACT = 2 (2 Clock Cycles)...................................................................................... 14-52
ACTTORW = 2 (2 Clock Cycles)....................................................................................... 14-52
CL = 2 (2 Clock Cycles) ..................................................................................................... 14-53
WRC = 2 (2 Clock Cycles) ................................................................................................. 14-53
RFRC = 4 (6 Clock Cycles) ................................................................................................ 14-54
BUFCMD = 1, LCRR[BUFCMDC] = 2............................................................................. 14-54
SDRAM Single-Beat Read, Page Closed, CL = 3 .............................................................. 14-55
SDRAM Single-Beat Read, Page Hit, CL = 3 .................................................................... 14-55
SDRAM Two-Beat Burst Read, Page Closed, CL = 3........................................................ 14-55
SDRAM Four-Beat Burst Read, Page Miss, CL = 3........................................................... 14-55
SDRAM Single-Beat Write, Page Hit................................................................................. 14-56
SDRAM Three-Beat Write, Page Closed............................................................................ 14-56
TRLX = 0) ...................................................................................................................... 14-40
EHTR = 0, TRLX = 1) ................................................................................................... 14-41
CSNT = 0, TRLX = 1) ................................................................................................... 14-42
(XACS = 0, ACS = 10, SCY = 0, CSNT = 1, TRLX = 1) ............................................. 14-42
(XACS = 0, ACS = 00, SCY = 1, CSNT = 1, TRLX = 1) ............................................. 14-43
1-Cycle Extended Hold Time on Reads)........................................................................ 14-44
(TRLX = 1, EHTR = 0, 4-Cycle Extended Hold Time on Reads) ................................. 14-45
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
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Freescale Semiconductor
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