MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 1185

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Table 19-19
19.4.1.17 System Version Register (SVR)
Shown in
This value can also be read though the SVR SPR of the e500 core. See
Register (SVR).” Section 5.2, “e500 Processor and System Version Numbers,”
for the MPC8544E.
Table 19-20
Freescale Semiconductor
32–47 Version A 16-bit number that identifies the version of the processor. Different version numbers indicate major
48–63 Revision A 16-bit number that distinguishes between implementations of the version. Different revision numbers
Bits
Offset 0xE_00A0
Offset 0xE_00A4
Reset 1
Reset 1
0–31
W
W
Bits
R
R
0
Name
0
Figure
0
0
describes the fields of PVR.
describes the fields of SVR.
Name
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
0
0
SV
differences between processors, such as which optional facilities and instructions are supported. (See
Section 5.2, “e500 Processor and System Version
indicate minor differences between processors having the same version number, such as clock rate and
engineering change level. (See
values.)
19-17, the SVR contains the system version number for the MPC8544E implementation.
0
0
0
0
System version numbers for the MPC8544E system logic
0x803_C_01_10 for MPC8544E with security
0x803_4_01_10 for MPC8544 without security
0
0
0
0
Version
Figure 19-16. Processor Version Register (PVR)
0
0
Figure 19-17. System Version Register (SVR)
0
0
Table 19-19. PVR Field Descriptions
Table 19-20. SVR Field Descriptions
0
0
1
1
0
1
Section 5.2, “e500 Processor and System Version
0
n
0
n n
System Version
0
15 16
1
n
Description
0
n n
Description
Numbers,” for specific values.)
0
0
n
0
n n
0
Section 6.5.4, “System Version
0
n
0
n n
Revision
0
lists the complete values
0
n
Numbers,” for specific
0
n n
0
Access: Read only
Access: Read only
1
n
0
n n
Global Utilities
0
0
n
19-19
31
31
0
n