MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 177

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

4.4.3.11
The eTSEC width input, shown in
Ethernet controller interface. Note that the value latched on this signal during POR is accessible through
the memory-mapped PORDEVSR (POR device status register) described in
Device Status Register (PORDEVSR).”
This input does not affect the width of the FIFO interface which is always an 8-bit FIFO interface.
4.4.3.12
The eTSEC3 width input, shown in
Ethernet controller interface 3. Note that the value latched on this signal during POR is accessible through
the memory-mapped PORDEVSR (POR device status register) described in
Device Status Register (PORDEVSR).”
The value of this configuration setting does not affect the width of the FIFO interface on eTSEC3, which
is always 8 bits.
4.4.3.13
The eTSEC1 protocol inputs, shown in
the eTSEC1 controller. Note that the value latched on these signals during POR is accessible through the
memory-mapped PORDEVSR (POR device status register) described in
Status Register (PORDEVSR).”
Freescale Semiconductor
TSEC1_TX_ER
TSEC3_TX_ER
Functional
Default (1)
Functional
Default (1)
Signal
Signal
eTSEC1 width
eTSEC3 Width
eTSEC1 Protocol
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Reset Configuration
Reset Configuration
cfg_tsec1_reduce
cfg_tsec3_reduce
Name
Name
Table 4-20. eTSEC1/eTSEC2 Width Configuration
Table 4-21. eTSEC3/eTSEC4 Width Configuration
Table
(Binary)
(Binary)
Table
Value
Value
0
1
0
1
Table
4-20, selects standard versus reduced width for three-speed
4-21, selects standard versus reduced width for three-speed
eTSEC3 Ethernet interface operates in reduced mode, either RTBI, RGMII
or RMII, or 8-bit FIFO mode.
eTSEC3 Ethernet interface operates in standard TBI, GMII, MII, or 8-bit
FIFO mode.
(default).
eTSEC1 interface operates in reduced pin mode, either RTBI, RGMII,
RMII, or in 8-bit FIFO mode.
eTSEC1 interface operates in standard width TBI, GMII, MII, or in 8-bit
FIFO mode.
(default)
4-22, select the protocol (FIFO, MII, GMII or TBI) used by
Meaning
Meaning
Section 19.4.1.4, “POR Device
Section 19.4.1.4, “POR
Section 19.4.1.4, “POR
Reset, Clocking, and Initialization
4-19