MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 879

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

The definition of the 8-byte received preamble sequence is shown in
The fields of the received preamble sequence are described in
be shorter than the 7-octet sequence defined by IEEE Std. 802.3, initial bytes of the received preamble
sequence hold undefined values. The standard start of frame delimiter (0xD5) is always omitted. Note that
preamble extraction is not possible in RMII mode.
15.6.3.6
By using promiscuous mode, the eTSEC can automatically gather network statistics required for remote
network interface monitoring. The RMON MIB group 1, RMON MIB group 2, RMON MIB group 3,
RMON MIB group 9, RMON MIB2, and the 802.3 Ethernet MIB are supported. For RMON statistics and
their corresponding counters, see the memory map.
15.6.3.7
The Ethernet controller performs frame recognition using destination address (DA) recognition. A frame
can be rejected or accepted based on the outcome.
15.6.3.7.1
The eTSEC can perform layer 2 frame filtering on the basis of destination Ethernet address (DA), as
illustrated by the flowchart in
Freescale Semiconductor
Bytes
Byte Offsets
0–1
2–3
4–5
6–7
0–1
2–3
4–5
6–7
8–15
8–15
8–15
8–15
Bits
0–7
0–7
0–7
0–7
RMON Support
Frame Recognition
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Destination Address Recognition and Frame Filtering
PreOct0 Octet #0 of received preamble. This is the first octet of preamble received.
PreOct1 Octet #1 of received preamble. This is the second octet of preamble received.
PreOct2 Octet #2 of received preamble. This is the third octet of preamble received.
PreOct3 Octet #3 of received preamble. This is the fourth octet of preamble received.
PreOct4 Octet #4 of received preamble. This is the fifth octet of preamble received.
PreOct5 Octet #5 of received preamble. This is the sixth octet of preamble received.
PreOct6 Octet #6 of received preamble. This is the seventh octet of preamble received. The last octet (the
0
Name
—
1
Figure 15-126. Definition of Received Preamble Sequence
start of frame delimiter) is discarded.
Reserved
Table 15-132. Received Preamble Field Descriptions
2
Figure
PreOct0
PreOct2
PreOct4
PreOct6
3
15-127.
4
5
6
7
Description
Table
8
9
15-132. Should the received preamble
Figure
Enhanced Three-Speed Ethernet Controllers
10
15-126.
11
PreOct1
PreOct3
PreOct5
12
13
14
15-147
15