MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 1148

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PCI Express Interface Controller
18.3.10.17 PCI Express Subsystem Vendor ID Update Register (EP Mode
The PCI Express subsystem vendor ID update register, shown in
for the Subsystem ID and Subsystem Vendor ID registers in the Type 0 configuration header.
The fields of the PCI Express subsystem vendor ID update register are described in
When used as an endpoint, the controller’s initialization software programs the desired subsystem ID and
subsystem vendor ID values in PEX_SSVID_UPDATE before setting the CFG_READY bit in the
PEX_CFG_READY register (see
way, when the host begins system enumeration, the correct values will be present in the Type 0
configuration header.
18.3.10.18 Configuration Ready Register—0x4B0
The PCI Express configuration ready register, shown in
complete status to the transaction layer. The transaction layer handles configuration requests from external
hosts only after the CFG_READY bit is set. All the configuration requests received from external hosts
before the CFG_READY bit is set are completed with configuration request retry status (CRS). The
CFG_READY bit in this register should be set after all relevant configuration registers have been
programmed. This makes sure the external host reads the correct capability advertisements during
enumeration.
Note that the state of PEX_CFG_READY[CFG_READY] is dependent upon the POR configuration
settings described
Configuration.”
18-94
31–16
15–0
Bits
Offset 0x4B0
Reset
Offset 0x478 (EP-mode only)
Reset 0
W
R
W
R
31
31
Figure 18-118. PCI Express Subsystem Vendor ID Update Register (PEX_SSVID_UPDATE)
0
SSV_ID
SS_ID
Name
Only)—0x478
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Figure 18-119. PCI Express Configuration Ready Register (PEX_CFG_READY)
0
0
inSection 4.4.3.5, “Host/Agent Configuration,”
0
0
Table 18-113. PEX_SSVID_UPDATE Field Descriptions
Subsystem ID [15–0] value
Subsystem vendor ID [15–0] value
0
SS_ID
0
0
Section 18.3.10.18, “Configuration Ready
0
0
0
0000_000 n (defined during POR)
0
0
—
0
16 15
0
Figure
0
0
Description
0
18-119, is used to indicate configuration
Figure
0
and
0
Section 4.4.3.7, “CPU Boot
0
18-118, is used to set the values
0
SSV_ID
Register—0x4B0”). That
0
0
0
Table
Freescale Semiconductor
0
Access: Red/Write
0
1
18-113.
Access: Mixed
CFG_READY
0
0
0
0
0
0