MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 375

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

14 x 10
14 x 10
13 x 10
13 x 10
Chip select interleaving is supported for the memory controller, and is programmed in
DDR_SDRAM_CFG[BA_INTLV_CTL]. Interleaving is supported between chip selects 0 and 1 or chip
selects 2 and 3. In addition, interleaving between all four chip selects can be enabled. When interleaving
is enabled, the chip selects being interleaved must use the same size of memory. If two chip selects are
interleaved, then 1 extra bit in the address decode is used for the interleaving to determine which chip
select to access. If four chip selects are interleaved, then two extra bits are required in the address decode.
Table 9-44
Table 9-45
Freescale Semiconductor
10 x 2
9 x 2
x 3
x 2
x 3
x 2
13 x
13 x
Row
Col
Row
Table 9-43. DDR2 Address Multiplexing for 32-Bit Data Bus with Interleaving Disabled (continued)
Col
x
x
MRAS
MCAS
MRAS
MCAS
MRAS
MCAS
MRAS
MCAS
MRAS
MCAS
MRAS
MCAS
MBA
MBA
MBA
MBA
MBA
MBA
Table 9-44. Example of Address Multiplexing for 64-Bit Data Bus Interleaving Between
illustrates examples of address decode when interleaving between two chip selects, and
shows examples of address decode when interleaving between four chip selects.
msb
msb
4
4
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
13 12 11 10 9 8 7 6 5 4 3 2 1 0
5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34–35
5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
13 12 11 10 9 8 7 6 5 4 3 2 1
12 11 10 9
12 11 10 9
12 11 10 9
12 11 10 9
8
7
8
6
7
8
5
6
7
8
4
5
Address from Core Master
6
7
Address from Core Master
3
4
Two Banks
5
6
2
3
4
5
1
2
3
4
0
1
SEL
SEL
2
3
CS
CS
0
0
1
2
SEL
SEL
CS
CS
20 21 22 23 24 25 26 27 28 29 30 31 32 33–35
0
1
2
2
1
0
1 0
1 0
1
1
0
1
0
0
9
0
9 8 7 6 5 4 3 2 1 0
9 8 7 6 5 4 3 2 1 0
9
9
8
8
8
8
7
7
7
7
6
6
6
6
5
5
5
5
4
4
DDR Memory Controller
4
4
3
3
3
3
2
2
2
2
1
1
1
1
0
0
0
0
lsb
9-51
lsb