MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 170

MPU POWERQUICC III 783-PBGA

MPC8544VTALF

Manufacturer Part Number
MPC8544VTALF
Description
MPU POWERQUICC III 783-PBGA
Manufacturer
Freescale Semiconductor
Datasheets

Specifications of MPC8544VTALF

Processor Type
MPC85xx PowerQUICC III 32-Bit
Speed
667MHz
Voltage
1V
Mounting Type
Surface Mount
Package / Case
783-FCPBGA
Processor Series
MPC85xx
Core
e500
Data Bus Width
32 bit
Maximum Clock Frequency
667 MHz
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Data Ram Size
32 KB
I/o Voltage
1.8 V, 3.3 V
Interface Type
I2C, HSSI, DUART
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MPC8544VTALF
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MPC8544VTALFA
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Reset, Clocking, and Initialization
4.4.3.2
Table 4-10
between the e500 core clock and the e500 core complex bus (CCB) clock. There is no default value for
this PLL ratio; these signals must be pulled to the desired values. Note that the values latched on these
signals during POR are accessible through the memory-mapped PORPLLSR, as described in
Section 19.4.1.1, “POR PLL Status Register (PORPLLSR),”
described in
4-12
LBCTL, LALE, LGPL2/LOE/LSDRAS
Functional Signals
describes the e500 core clock PLL inputs that program the core PLL and establish the ratio
Functional Signals
Section 6.10.2, “Hardware Implementation-Dependent Register 1 (HID1).”
No Default
e500 Core PLL Ratio
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
No Default
LA[28:31]
Reset Configuration
Table 4-10. e500 Core Clock PLL Ratios
cfg_sys_pll[0:3]
Reset Configuration Name Value (Binary)
Table 4-9. CCB Clock PLL Ratio
Name
cfg_core_pll[0:2]
(Binary)
Value
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
and also in the e500 core HID1 register, as
000
001
010
011
100
101
110
111
CCB Clock : SYSCLK Ratio
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
16 : 1
10 : 1
12 : 1
3 : 1
4 : 1
5 : 1
6 : 1
8 : 1
9 : 1
e500 Core: CCB ClockRatio
Freescale Semiconductor
3 : 2 (1.5 : 1)
7 : 2 (3.5 : 1)
5 : 2 (2.5:1)
Reserved
4 : 1
1 : 1
2 : 1
3 : 1

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