MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 147

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

TSEC3_GTX_CLK TSEC3 transmit clock out
Freescale Semiconductor
TSEC3_TXD[6:4]
TSEC3_TXD[1:0]
TSEC3_RXD[7:0]
TSEC3_RX_CLK
TSEC3_TX_CLK
TSEC3_RX_ER
TSEC3_TX_EN
TSEC3_TX_ER
TSEC3_RX_DV
TSEC3_TXD3
TSEC3_TXD2
TSEC3_CRS
TSEC3_COL
LAD[0:31]
LA[28:31]
LWE[1:3]/
LDP[0:3]
LCS[0:4]
LBS[1:3]
LBCTL
LGPL0
LGPL1
LGPL2
Name
LWE0
/LBS0
LCS5
LCS6
LCS7
LA27
LALE
/LOE
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Table 3-1. MPC8544E Signal Reference by Functional Block (continued)
TSEC3 transmit data [6:4]
TSEC3 transmit data 3
TSEC3 transmit data 2
TSEC3 transmit data 1–0
TSEC3 transmit enable
TSEC3 transmit error
TSEC3 transmit clock in
TSEC3 carrier sense
TSEC3 collision detect
TSEC3 receive data 7–0
TSEC3 receive data valid
TSEC3 receive error
TSEC3 receive clock
Local bus address/data
Local bus data parity
Local bus burst address
Local bus port address
Local bus chip select 0–4
Local bus chip select 5
Local bus chip select 6
Local bus chip select 7
Local bus write enable
/byte select 0
Local bus write enable
/byte select 1–3
Local bus data buffer control
Local bus address latch enable
Local bus UPM general purpose
line 0
Local bus GP line 1
Local bus GP line 2
/output enable
Description
Functional
eTSEC3
eTSEC3
eTSEC3
eTSEC3
eTSEC3
eTSEC3
eTSEC3
eTSEC3
eTSEC3
eTSEC3
eTSEC3
eTSEC3
eTSEC3
eTSEC3
Block
LBC
LBC
LBC
LBC
LBC
LBC
LBC
LBC
LBC
LBC
LBC
LBC
LBC
LBC
LBC
Alternate Function(s)
cfg_etsec3_prtcl[1:0]
cfg_etsec3_reduce
/cfg_io_ports[0:2]
cfg_etsec3_serial
cfg_dram_type[0]
cfg_dram_type[1]
cfg_gpinput[0:31]
cfg_host_agt[0:2]
FIFO3_RXD[7:0]
FIFO3_TXD[6:4]
FIFO3_TXD[1:0]
FIFO3_TX_CLK
FIFO3_RX_CLK
DMA_DDONE2
cfg_sys_pll[0:3]
FIFO3_RX_FC
FIFO3_RX_DV
FIFO3_RX_ER
FIFO3_TX_EN
FIFO3_TX_ER
FIFO3_TX_FC
cfg_core_pll[0]
cfg_core_pll[1]
cfg_core_pll[2]
DMA_DREQ2
cfg_cpu_boot
DMA_DACK2
FIFO3_TXD3
FIFO3_TXD2
—
—
—
—
Signals
No. of
32
3
1
1
2
1
1
1
1
1
1
8
1
1
1
4
1
4
5
1
1
1
1
3
1
1
1
1
1
I/O
I/O
I/O
I/O
I/O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
Signal Descriptions
15-2/15-9
15-2/15-9
15-2/15-9
15-2/15-9
15-2/15-9
15-2/15-9
15-2/15-9
15-2/15-9
15-2/15-9
15-2/15-9
15-2/15-9
15-2/15-9
15-2/15-9
15-2/15-9
14-2/14-5
14-2/14-5
14-2/14-5
14-2/14-5
14-2/14-5
14-2/14-5
14-2/14-5
14-2/14-5
14-2/14-5
14-2/14-5
14-2/14-5
14-2/14-5
14-2/14-5
14-2/14-5
14-2/14-5
Table/
Page
3-7