MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 226

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Core Register Summary
1
6.3
The following sections describe general-purpose and integer exception registers.
6.3.1
GPR0–GPR31 support integer operations. The instruction formats provide 5-bit fields for specifying the
GPRs to be used in the execution of the instruction. Each GPR is a 64-bit register, although only 64-bit
load, store, and merge instructions use GPR bits 0–31.
6.3.2
6-8
Abbreviation
Reset
Accesses to this register requires synchronization, as described in the “Synchronization Requirements” section of the
“Register Model” chapter of the PowerPC™ e500 Core Family Reference Manual .
SPR 1
SPEFSCR
TLB0CFG
TLB1CFG
W
PID0
PID1
PID2
R
SPR
SVR
SO
32
Registers for Computational Operations
OV
General-Purpose Registers (GPRs)
Integer Exception Register (XER)
Process ID register 0
Process ID register 1
Process ID register 2
Signal processing and embedded floating-point
status and control register
System version register
TLB configuration register 0
TLB configuration register 1
33
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Register fields designated as write-one-to-clear are cleared only by writing
ones to them. Writing zeros to them has no effect.
CA
34
Table 6-2. Additional SPRs (by SPR Abbreviation) (continued)
35
Figure 6-2. Integer Exception Register (XER)
Name
1
1
1
1
NOTE
All zeros
—
SPR Number
1023
633
634
512
688
689
48
Read/Write
Read/Write
Read/Write
Read/Write
Read only
Read only
Read only
Access
Supervisor
56 57
Only
Freescale Semiconductor
Yes
Yes
Yes
Yes
Yes
Yes
No
Access: User read/write
Number of bytes
6.12.4.2/6-34
6.12.1/6-32
6.12.4/6-33
6.5.4/6-14
6.14/6-45
Section/
Page
63