MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 769

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Table 15-14
15.5.3.2
This section describes the control and status registers that are used specifically for transmitting Ethernet
frames. All of the registers are 32 bits wide.
15.5.3.2.1
This register is writable by the user to configure the transmit block.
register.
Table 15-15
Freescale Semiconductor
Offset eTSEC1:0x2_4100; eTSEC3:0x2_5100
Reset
27–31
0–16
0–26
Bits
Offset eTSEC1:0x2_4030; eTSEC3:0x2_5030
Reset
Bits
17
W
R
W
R
0
0
Name
TBIPA This field is used to program the PHY address of the ten-bit interface’s MII management bus. To access the
IPCSEN
—
Name
—
describes the fields of the TBIPA register.
describes the fields of the TCTRL register.
eTSEC Transmit Control and Status Registers
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Transmit Control Register (TCTRL)
Reserved
TBI register the user must write the TBIPA value to the MIIMADD [PHY Address] register located in the MAC
register section. PHY Address 0 is reserved. Refer to
(MIIMADD).”
—
Reserved
IP header checksum generation enable. When set, the eTSEC offloads IPv4 header checksum
generation. See
0 IP header checksum generation is disabled even if enabled in a transmit frame control block.
1 IP header checksum generation is performed for IPv4 headers as determined by the settings in the
current transmit frame control block.
16
IPCSEN TUCSEN VLINS THDF
17
Figure 15-11. TCTRL Register Definition
Section 15.6.4.2, “Transmit Path Off-Load,” on page
Figure 15-10. TBIPA Register Definition
Table 15-15. TCTRL Field Descriptions
Table 15-14. TBIPA Field Descriptions
18
—
19
All zeros
All zeros
20
Description
Description
Section 15.5.3.5.8, “MII Management Address Register
21
—
26
Figure 15-11
RFC_PAUSE
Enhanced Three-Speed Ethernet Controllers
27
15-158.
describes the TCTRL
TFC_PAUSE TXSCHED —
28
26 27
Access: Read/Write
Access: Mixed
TBIPA
29
30
15-37
31
31