MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 913

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Table 15-149
Table 15-150
Freescale Semiconductor
eTSEC Signals
GTX_CLK125
MDIO
MDC
describes the shared signals of the MII interface.
describes the register initializations required to configure the eTSEC in MII mode.
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Sum
(This example has Full Duplex = 0, Preamble count = 7, PAD/CRC append = 1)
Table 15-148. MII Interface Mode Signal Configuration (continued)
I/O
I/O
O
MACSTNADDR2[0110_0000_0000_0010_0000_0000_0000_0000]
MACSTNADDR1[0100_0011_0110_0101_1000_0111_1000_1100]
I
Signals
RX_ER
RX_DV
MACCFG1[1000_0000_0000_0000_0000_0000_0000_0000]
MACCFG1[0000_0000_0000_0000_0000_0000_0000_0000]
MACCFG2[0000_0000_0000_0000_0111_0001_0000_0100]
COL
CRS
Table 15-150. MII Mode Register Initialization Steps
ECNTRL[0000_0000_0000_0000_0001_0000_0000_0000]
Set station address to 02_60_8C_87_65_43, for example.
Set station address to 02_60_8C_87_65_43, for example.
Signals
No. of
Sum
eTSEC Signals
Initialize MACCFG2, for MII, half duplex operation.
1
1
1
(This example has Statistics Enable = 1)
Table 15-149. Shared MII Signals
Initialize MAC Station Address,
Initialize MAC Station Address,
I/O
I
I
I
I
MII Signals
not used
MDIO
MDC
Initialize ECNTRL,
Clear Soft_Reset,
Set I/F Mode bit,
Set Soft_Reset,
Signals
No. of
Sum
25
1
1
1
1
I/O
I/O
O
Signals
RX_ER
RX_DV
I
COL
CRS
Frequency [MHz] 25
Sum
Signals
Voltage [V] 3.3
No. of
MII Interface
1
1
0
I/O
Enhanced Three-Speed Ethernet Controllers
I
I
I
I
Management interface clock
Management interface I/O
Signals
No. of
16
1
1
1
1
Reference clock
Function
15-181