MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 607

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

13.3.1.6
The UFCR, a write-only register, is used to enable and clear the receiver and transmitter FIFOs, set a
receiver FIFO trigger level to control the received data available interrupt, and select the type of DMA
signaling.
When the UFCR bits are written, the FIFO enable bit must also be set or else the UFCR bits are not
programmed. When changing from FIFO mode to 16450 mode (non-FIFO mode) and vice versa, data is
automatically cleared from the FIFOs.
After all the bytes in the receiver FIFO are cleared, the receiver internal shift register is not cleared.
Similarly, the bytes are cleared in the transmitter FIFO, but the transmitter internal shift register is not
cleared. Both TFR and RFR are self-clearing bits.
Figure 13-8
Freescale Semiconductor
IID[3–0]
IID Bits
0b1100
0b0010
0b0000
Offset 0x502
Reset
W
Priority
Second
R
Fourth
Level
Third
shows the bits in the UFCRs.
0x602
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
FIFO Control Registers (UFCR0, UFCR1) (ULCR[DLAB] = 0)
0
Character time-out
UTHR empty
Modem status
Interrupt Type
RTL
Figure 13-8. FIFO Control Registers (UFCR0, UFCR1)
Table 13-11. UIIR IID Bits Summary (continued)
1
No characters have been removed from or
input to the receiver FIFO during the last 4
character times and there is at least one
character in the receiver FIFO during this time.
Transmitter holding register is empty
CTS input value changed since last read of
UMSR
2
—
Interrupt Description
3
All zeros
DMS
4
TFR
5
Read the receiver buffer register.
Read the UIIR or write to the
UTHR.
Read the UMSR.
How To Reset Interrupt
RFR
6
Access: Write only
FEN
7
DUART
13-11