MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 575

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

12.5.1.2
These registers contains status fields and counters which provide the user with status information
regarding the channel’s actual processing of a given descriptor.
Table 12-52
Freescale Semiconductor
12–15
16–19
20–23
24–31
32–37
8–10
Bits
0–2
3–7
Address Channel_1 0x01110
Reset
Reset
FF_COUNTER Fetch FIFO counter. This 5 bit counter indicates how many fetch pointers are currently stored in the
W
W
R
R
CHN_STATE
G_STATE
S_STATE
Channel_2 0x01210
Channel_3 0x01310
Channel_4 0x01410
32
0
Name
—
—
—
—
—
describes the channel pointer status register fields.
Crypto-Channel Pointer Status Registers 1–4 (CCPSR n )
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
2
—
Table 12-52. Crypto-Channel Pointer Status Register Field Descriptions
3
FF_COUNTER
Reserved.
FIFO.
Reserved.
The value of this field indicates which stage the channel is while performing gather function.
Table 12-53
Note: G_State is documented for information only. The user will not typically care about the gather
Reserved.
The value of this field indicates which stage the channel is while performing scatter function.
Table 12-53
Note: S_State is documented for information only. The user will not typically care about the scatter
machine. The value of this field indicates exactly which stage the channel is in the sequence of fetching
and processing data descriptors.
field.
Note: CHN_State is documented for information only. The user will not typically care about the channel
Reserved, set to zero
Gather state machine state. This field reflects the state of the channel gather control state machine.
Scatter state machine state. This field reflects the state of the channel scatter control state machine.
State. State of the channel state machine. This field reflects the state of the channel control state
37 38
state machine.
state machine.
state machine.
Figure 12-74. Crypto-Channel Pointer Status Register
MI MO PR SR PG SG PRD SRD PD SD
39
7
shows the meaning of all possible values of the G_STATE field.
shows the meaning of all possible values of the S_STATE field.
40
8
41
—
42
11
43
Table 12-54
12
44
G_STATE
All zeros
All zeros
45
Description
46
shows the meaning of all possible values of the STATE
15 16
47 48
—
19 20
S_STAT
Error
E
23 24
Security Engine (SEC) 2.1
CHN_STATE
Access: Read-only
59 60
PTR_DW
12-95
31
63