MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 829

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

15.5.3.6.34 Transmit Late Collision Packet Counter (TLCL)
Figure 15-85
Table 15-88
15.5.3.6.35 Transmit Excessive Collision Packet Counter (TXCL)
Figure 15-86
Table 15-89
Freescale Semiconductor
20–31
0–19
Bits
Offset
Reset
Offset
Reset
20–31
0–19
Bits
W
W
R
R
Name
TLCL
0
0
eTSEC1:0x2_4704; eTSEC3:0x2_5704
eTSEC1:0x2_4708; eTSEC3:0x2_5708
—
describes the fields of the TLCL register.
describes the fields of the TXCL register.
Name
TXCL
describes the definition for the TLCL register.
describes the definition for the TXCL register.
Figure 15-86. Transmit Excessive Collision Packet Counter Register Definition
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
—
Reserved
Transmit late collision packet counter. Increments for each frame transmitted which experienced a late
collision during a transmission attempt. Late collisions are defined using the collision window field of the
half-duplex [26:31] register.
Figure 15-85. Transmit Late Collision Packet Counter Register Definition
Reserved
collisions during transmission and was aborted.
Transmit excessive collision packet counter. Increments for each frame that experienced 16
Table 15-89. TXCL Field Descriptions
Table 15-88. TLCL Field Descriptions
—
—
All zeros
All zeros
Description
Description
19 20
19 20
Enhanced Three-Speed Ethernet Controllers
TXCL
TLCL
Access: Read/Write
Access: Read/Write
15-97
31
31