MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 779

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Table 15-21
15.5.3.2.8
The TBDBPH register is written by the user with the most significant address bits common to all TxBD
buffer addresses, TxBD[Data Buffer Pointer]. As a consequence, all Tx buffers must be placed in a 4
gigabyte segment of memory whose base address is prefixed by the bits in TBDBPH. The TxBD ring itself
can reside in a different memory region (based at TBASEH).
TBDBPH register.
Table 15-24
15.5.3.2.9
TBPTR0–TBPTR7 each contains the low-order 32 bits of the next transmit buffer descriptor address for
their respective TxBD ring.
of their ring’s associated TBASE when the TBASE register is written by software. Software must not write
TBPTR0–TBPTR7 while eTSEC is actively transmitting frames. However, TBPTR0– TBPTR7 can be
modified when the transmitter is disabled or when no Tx buffer is in use (after a GRACEFUL STOP
Freescale Semiconductor
16–23
24–31
28–31
8–15
0–27
Bits
Bits
0–7
Offset
Reset
W
R
Name
TBDBPH Most significant bits common to all data buffer addresses contained in TxBDs. The user must initialize
WT5
WT6
WT7
WT4
0
Name
eTSEC1:0x2_4180; eTSEC3:0x2_5180
—
describes the fields of the TR47WT register.
describes the fields of the TBDBPH register.
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Transmit Data Buffer Pointer High Register (TBDBPH)
Transmit Buffer Descriptor Pointers 0–7 (TBPTR0–TBPTR7)
Weighting value for TxBD ring 4 when TCTRL[TXSCHED] = 10. On each round of the Tx scheduler, a
minimum of WT4 × 64 bytes of data are scheduled for transmission from TxBD ring 4. Clearing this field
prevents transmission.
Weighting value for TxBD ring 5 when TCTRL[TXSCHED] = 10. On each round of the Tx scheduler, a
minimum of WT5 × 64 bytes of data are scheduled for transmission from TxBD ring 5. Clearing this field
prevents transmission.
Weighting value for TxBD ring 6 when TCTRL[TXSCHED] = 10. On each round of the Tx scheduler, a
minimum of WT6 × 64 bytes of data are scheduled for transmission from TxBD ring 6. Clearing this field
prevents transmission.
Weighting value for TxBD ring 7 when TCTRL[TXSCHED] = 10. On each round of the Tx scheduler, a
minimum of WT7 × 64 bytes of data are scheduled for transmission from TxBD ring 7. Clearing this field
prevents transmission.
Reserved
TBDBPH before enabling the eTSEC transmit function.
Figure 15-19
Figure 15-18. TBDBPH Register Definition
Table 15-22. TBDBPH Field Descriptions
Table 15-21. TR47WT Field Descriptions
describes the TBPTR registers. These registers takes on the value
—
All zeros
Description
Description
Figure 15-18
Enhanced Three-Speed Ethernet Controllers
describes the definition for the
Access: Read/Write
27 28
TBDBPH
15-47
31