MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 61

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Figure
Number
17-38
17-39
17-40
17-41
17-42
17-43
17-44
17-45
17-46
17-47
17-48
17-49
17-50
17-51
17-52
17-53
17-54
17-55
17-56
17-57
17-58
17-59
17-60
17-61
17-62
17-63
17-64
17-65
18-1
18-2
18-3
18-4
18-5
18-6
18-7
18-8
18-9
18-10
18-11
18-12
Freescale Semiconductor
64-Bit High Memory Base Address Register ..................................................................... 17-38
PCI Subsystem Vendor ID Register .................................................................................... 17-38
PCI Subsystem ID Register................................................................................................. 17-39
PCI Bus Capabilities Pointer Register ................................................................................ 17-39
PCI Bus Interrupt Line Register.......................................................................................... 17-39
PCI Bus Interrupt Pin Register............................................................................................ 17-40
PCI Bus Minimum Grant Register (MIN_GNT) ................................................................ 17-40
PCI Bus Maximum Latency Register (MAX_LAT) ........................................................... 17-41
PCI Bus Function Register.................................................................................................. 17-41
PCI Bus Arbiter Configuration Register ............................................................................. 17-42
PCI Arbitration Example .................................................................................................... 17-44
PCI Single-Beat Read Transaction...................................................................................... 17-51
PCI Burst Read Transaction................................................................................................ 17-51
PCI Single-Beat Write Transaction..................................................................................... 17-52
PCI Burst Write Transaction ............................................................................................... 17-52
PCI Target-Initiated Terminations....................................................................................... 17-55
DAC Single-Beat Read Example........................................................................................ 17-57
DAC Burst Read Example .................................................................................................. 17-57
DAC Single-Beat Write Example ....................................................................................... 17-58
DAC Burst Write Example ................................................................................................. 17-58
Standard PCI Configuration Header ................................................................................... 17-59
PCI Type 0 Configuration Translation ................................................................................ 17-62
PCI Parity Operation........................................................................................................... 17-65
Address Invariant Byte Ordering—4 bytes Outbound........................................................ 17-69
Address Invariant Byte Ordering—4 bytes Inbound .......................................................... 17-69
Address Invariant Byte Ordering—8 bytes Outbound........................................................ 17-70
Address Invariant Byte Ordering—2 bytes Inbound .......................................................... 17-70
CFG_DATA Byte Ordering................................................................................................. 17-70
PCI Express Controller Block Diagram................................................................................ 18-2
PCI Express Configuration Address Register (PEX_CONFIG_ADDR) ............................. 18-9
PCI Express Configuration Data Register (PEX_CONFIG_DATA) .................................. 18-10
PCI Express Outbound Completion Timeout Register (PEX_OTB_CPL_TOR)............... 18-11
PCI Express Configuration Retry Timeout Register (PEX_CONF_RTY_TOR) ............... 18-11
PCI Express Configuration Register (PEX_CONFIG) ....................................................... 18-12
PCI Express PME and Message Detect Register (PEX_PME_MES_DR)......................... 18-13
PCI Express PME and Message Disable Register (PEX_PME_MES_DISR) ................... 18-14
PCI Express PME and Message Interrupt Enable
PCI Express Power Management Command Register (PEX_PMCR) ............................... 18-17
IP Block Revision Register 1 .............................................................................................. 18-18
IP Block Revision Register 2 .............................................................................................. 18-19
Register (PEX_PME_MES_IER) .................................................................................. 18-16
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
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