MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 538

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Security Engine (SEC) 2.1
12.4.4.8
The MDEU interrupt control register, shown in
given error (as defined in
corresponding bit in this register is set, then the error is disabled; no error interrupt occurs and the interrupt
status register is not updated to reflect the error. If the corresponding bit is not set, then upon detection of
an error, the interrupt status register is updated to reflect the error, causing assertion of the error interrupt
signal, and causing the module to halt processing.
Table 12-33
12-58
Address MDEU 0x3_6038
58–60
62–63
0–48
Bits
Bits
61
Reset
49
50
51
52
53
W
R
Name
0
IFO
—
—
Name
describes MDEU interrupt status register fields.
ERE
ICE
CE
MDEU Interrupt Control Register (MDEUICR)
—
—
IE
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Reserved
Input FIFO overflow. The MDEU input FIFO was pushed while full.
0 No overflow detected
1 Input FIFO has overflowed
Note: When operated through channel-controlled access, the SEC implements flow control, and FIFO size is
Reserved
Table 12-32. MDEU Interrupt Status Register Field Descriptions (continued)
not a limit to data input size. When operated through host-controlled access, the MDEU cannot accept
FIFO inputs larger than 256 bytes without overflowing.
Table 12-33. MDEU Interrupt Control Register Field Descriptions
Reserved
Integrity check error. The supplied ICV did not match the one computed by the MDEU.
0 Integrity check error enabled
1 Integrity check error disabled
Reserved
Internal error. An internal processing error was detected while performing hashing.
0 Internal error enabled
1 Internal error disabled
Early read error. The MDEU register was read while the MDEU was performing hashing.
0 Early read error enabled
1 Early read error disabled
Context error. The MDEU key register, the key size register, the data size register, or the mode
register, was modified while the MDEU was performing hashing.
0 Context error enabled
1 Context error disabled
Section 12.4.4.7, “MDEU Interrupt Status Register
—
Figure 12-36. MDEU Interrupt Control Register
Figure
48 49
0x3000
ICE — IE ERE CE KSE DSE ME AE
Description
12-36, controls the result of detected errors. For a
50 51
Description
52
53
54
(MDEUISR)”), if the
55
56
Freescale Semiconductor
57 58 59 60
Access: Read/Write
—
IFO
61
62 63
—