MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 393
![MPU POWERQUICC III 783-PBGA](/photos/37/62/376266/mpc8544e_image_sml.jpg)
MPC8544VTALF
Manufacturer Part Number
MPC8544VTALF
Description
MPU POWERQUICC III 783-PBGA
Manufacturer
Freescale Semiconductor
Datasheets
1.MPC8544VTALF.pdf
(117 pages)
2.MPC8544VTALF.pdf
(2 pages)
3.MPC8544VTALF.pdf
(1340 pages)
Specifications of MPC8544VTALF
Processor Type
MPC85xx PowerQUICC III 32-Bit
Speed
667MHz
Voltage
1V
Mounting Type
Surface Mount
Package / Case
783-FCPBGA
Processor Series
MPC85xx
Core
e500
Data Bus Width
32 bit
Maximum Clock Frequency
667 MHz
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Data Ram Size
32 KB
I/o Voltage
1.8 V, 3.3 V
Interface Type
I2C, HSSI, DUART
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC8544VTALF
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MPC8544VTALFA
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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9.6.1
Depending on the memory type used, certain fields must be programmed differently.
the differences in certain fields for different memory types. Note: This table does not list all fields that must
be programmed.
Freescale Semiconductor
DDR_SDRAM_CLK_CNTL Clock adjust
DDR_SDRAM_INTERVAL
DDR_SDRAM_MODE_2
ODT_RD_CFG
DDR_INIT_EXT_ADDR
DDR_SDRAM_CFG_2
DDR_SDRAM_MODE
Parameter
DDR_SDRAM_CFG
DDR_INIT_ADDR
AP n _EN
DDR_DATA_INIT
Table 9-53. Memory Interface Configuration Register Initialization Parameters (continued)
Name
Programming Differences Between Memory Types
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Chip Select n Auto
Precharge Enable
Chip Select ODT Read
Configuration
Table 9-54. Programming Differences Between Memory Types
Description
Control configuration
Control configuration
Mode configuration
Mode configuration
Interval configuration
Data initialization configuration
register
Initialization address
Extended initialization address
Description
DDR1
DDR2
DDR1
DDR2
Can be used to place chip select n in auto
precharge mode
Can be used to place chip select n in auto
precharge mode
Should always be set to 000
could be set differently depending on system
topology. However, systems with only 1 chip select
will typically not use ODT when issuing reads to
the memory.
Can be enabled to assert ODT if desired. This
SDRAM_TYPE
DLL_RST_DIS
DYN_PWR
DQS_CFG
Differences
ODT_CFG
ECC_EN
RD_EN
32_BE
SR_IE
SREN
8_BE
DBW
INIT_EXT_ADDR
CLK_ADJUST
ESDMODE2
ESDMODE3
INIT_VALUE
INIT_ADDR
ESDMODE
Parameter
BSTOPRE
SDMODE
REFINT
BA_INTLV_CTL
NUM_PR
x32_EN
2T_EN
D_INIT
NCAP
HSE
BI
Table 9-54
DDR Memory Controller
Section/page
Section/page
9.4.1.2/9-11
9.4.1.2/9-11
9.4.1.10/9-26
9.4.1.12/9-29
9.4.1.13/9-29
9.4.1.14/9-30
9.4.1.15/9-30
9.4.1.16/9-31
9.4.1.7/9-20
9.4.1.8/9-23
9.4.1.9/9-25
illustrates
9-69
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