MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 701

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Figure 14-70
must simulate the electric characteristics of his scenario to determine the maximum operating frequency.
14.5.1.4
In case a system contains a memory hierarchy with high speed synchronous memories (SDRAM,
synchronous SRAM) and lower speed asynchronous memories (for example, Flash EPROM and
peripherals) the GPCM-controlled memories should be decoupled by buffers to reduce capacitive loading
on the bus. Those buffers have to be taken into account for the timing calculations.
GPCM address timings.
To calculate address setup timing for a slower peripheral/memory device, several parameters have to be
added: propagation delay for the address latch, propagation delay for the buffer and the address setup for
the actual peripheral. Typical values for the 2 propagation delays are in the order of 3–6 ns, so for a
166-MHz bus frequency, LCS should arrive on the order of 3 bus clocks later.
Freescale Semiconductor
shows an example of such a hierarchy. This section is only a guideline and the board designer
Local Bus Interface
Local Bus Interface
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
GPCM Timings
Figure 14-70. Local Bus Peripheral Hierarchy for Very High Bus Speeds
LAD[0:31]
LAD[0:31]
LA[27:31]
LBCTL
LBCTL
LALE
LALE
Figure 14-71. GPCM Address Timings
Muxed Address/Data
Non-Muxed Address
Latch
Buffered Data
A/D
LE
DIR
A
Latch
Q
B
Buffer
Muxed Address/Data
Non-Muxed Address
Buffered Address
A
DQ
A
MA
Device
Signal
Input
Peripherals
Memories
Slower
and
Peripherals
Memories
Figure 14-71
A
Slower
DQ
SDRAM
and
Local Bus Controller
shows the
14-81