MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 1054
![MPU POWERQUICC III 783-PBGA](/photos/37/62/376266/mpc8544e_image_sml.jpg)
MPC8544VTALF
Manufacturer Part Number
MPC8544VTALF
Description
MPU POWERQUICC III 783-PBGA
Manufacturer
Freescale Semiconductor
Datasheets
1.MPC8544VTALF.pdf
(117 pages)
2.MPC8544VTALF.pdf
(2 pages)
3.MPC8544VTALF.pdf
(1340 pages)
Specifications of MPC8544VTALF
Processor Type
MPC85xx PowerQUICC III 32-Bit
Speed
667MHz
Voltage
1V
Mounting Type
Surface Mount
Package / Case
783-FCPBGA
Processor Series
MPC85xx
Core
e500
Data Bus Width
32 bit
Maximum Clock Frequency
667 MHz
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Data Ram Size
32 KB
I/o Voltage
1.8 V, 3.3 V
Interface Type
I2C, HSSI, DUART
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC8544VTALF
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MPC8544VTALFA
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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PCI Bus Interface
Figure 17-63
invariance.
Figure 17-64
Note that in all of these examples, the original addresses of the individual bytes within the scalars (as
created by the source) have been preserved.
17.5.2.1
All internal memory-mapped registers in the CCSR space use big endian byte ordering. However, the PCI
specification defines PCI configuration registers as little endian. All accesses to the PCI configuration port,
CFG_DATA, including the those targeting the internal PCI configuration registers, use the address
invariance policy as shown in
little-endian formatted data—either by using the lwbrx/stwbrx instructions or by manipulating the data
before writing to and after reading from CFG_DATA.
17-70
Address lsbs
Significance
Byte lane
Data
Address lsbs
Significance
Byte lane
Data
Byte Order for Configuration Transactions
shows an outbound transfer of an 8-byte scalar, 0x5455_1617_CDCE_2728, using address
shows an inbound transfer of a 2-byte scalar, 0x5837, using address invariance.
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
PCI Configuration Space
MSB
000
54
0
Figure 17-63. Address Invariant Byte Ordering—8 bytes Outbound
Figure 17-64. Address Invariant Byte Ordering—2 bytes Inbound
001
55
1
Big endian source bus
CFG_DATA
010
16
2
011
—
3
011
Figure
17
Little endian
3
source bus
010
—
Figure 17-65. CFG_DATA Byte Ordering
2
CD CE
100
4
MSB LSB
001
58
17-65. Therefore, software must access CFG_DATA with
1
Byte0
Byte3
101
MSB
5
000
37
0
110
27
6
LSB
111
28
7
Byte1
Byte2
MSB
111
28
7
MSB LSB
000
37
0
destination bus
Little endian destination bus
110
27
6
Big endian
001
58
1
101
CE CD
5
Byte2
Byte1
010
—
2
100
4
011
—
3
011
17
3
010
16
2
Freescale Semiconductor
Byte3
Byte0
LSB
001
55
1
LSB
000
54
0
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