MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 1182

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Global Utilities
19.4.1.13 Power Management Control and Status Register (POWMGTCSR)
Shown in
for controlling when it wakes up. It also contains power management status bits. See
“Interrupts and Power Management Controlled by POWMGTCSR,”
Table 19-16
19-16
Offset 0xE_0080
Reset
2–11
Bits
Bits
29
30
31
12
13
0
1
W
R
IRQ_MSK CI_MSK
DUART Dual UART controller disabled
IRQ_MSK Interrupt input mask
Name
CI_MSK
Name
I2C
—
DOZ
Figure
0
—
—
describes the bit settings of POWMGTCSR.
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Figure 19-13. Power Management Control and Status Register (POWMGTCSR)
I
0 I
1 I
0 DUART enabled
1 DUART disabled
Reserved
2
C controllers disabled
19-13, POWMGTCSR contains bits for placing the MPC8544E into low power states and
Critical interrupt input mask
0 Interrupts cause the device to wake up from a low-power state.
1 Interrupts are masked as a wake-up condition. The device remains in a low-power state despite the
0 Critical interrupts cause the device to wake up from a low power state.
1 Critical interrupts are masked as a wake-up condition. The device remains in a low-power state despite
Reserved
Doze mode.
0 No request to put device in doze mode. Note that this bit is automatically cleared on MCP, UDE, SRESET,
1 Device is to be placed in doze mode. Instruction fetching is halted in the e500 core. Note that this bit is
Reserved
2
2
C controllers enabled
C controllers disabled
1
presence of an interrupt request.
the presence of a critical interrupt.
core_tbint (from the core) and also int and cint if not masked.
logically ORed with HID0[DOZE].
2
Table 19-15. DEVDISR Field Descriptions (continued)
Table 19-16. POWMGTCSR Field Descriptions
—
11
DOZ — SLP
12
13
14
All zeros
15
Description
Description
—
for more information.
27
DOZING NAPPING SLPING
28
Freescale Semiconductor
Section 19.5.1.8.2,
29
Access: Mixed
30
31
—