MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet

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... Provides an extensive instruction set for vector (64-bit) integer and fractional operations. These instructions use both the upper and lower words of the 64-bit GPRs as they are defined by the SPE APU. © 2010 Freescale Semiconductor, Inc. Document Number: MPC8544EEC Rev. 5, 01/2011 Contents 1. MPC8544E Overview . . . . . . . . . . . . . . . . . . . . . . . . . .1 2 ...

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... Three inbound windows plus a configuration window on PCI and PCI Express – Four outbound windows plus default translation for PCI and PCI Express • DDR/DDR2 memory controller — Programmable timing supporting DDR and DDR2 SDRAM — 64-bit data interface MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev Freescale Semiconductor ...

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... RSA and Diffie-Hellman; programmable field size up to 2048 bits – Elliptic curve cryptography with F 511 bits — DEU—Data Encryption Standard execution unit – DES, 3DES MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor m and F(p) modes and programmable field size MPC8544E Overview 3 ...

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... Up to eight-beat burst transfers — The 32-, 16-, and 8-bit port sizes are controlled by an on-chip memory controller. — Two protocol engines available on a per chip select basis: MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev addressing mode 2 C interface Freescale Semiconductor ...

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... Programmable Ethernet preamble insertion and extraction bytes — MAC address recognition: – Exact match on primary and virtual 48-bit unicast addresses – VRRP and HSRP support for seamless router fail-over – exact-match MAC addresses supported MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor MPC8544E Overview 5 ...

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... Supports PCI-to-memory and memory-to-PCI streaming — Memory prefetching of PCI read accesses — Supports posting of processor-to-PCI and PCI-to-memory writes — PCI 3.3-V compatible — Selectable hardware-enforced coherency MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev Freescale Semiconductor ...

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... Supports large block (4-Kbyte) uploads and downloads — Supports continuous bit streaming of entire block for fast upload and download • IEEE Std 1149.1™-compliant, JTAG boundary scan • 783 FC-PBGA package MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor MPC8544E Overview 7 ...

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... Table 1. Absolute Maximum Ratings Symbol 256-Kbyte L2 Cache 64-Bit e500 DDR/DDR2 Coherency SDRAM Module Controller PCI Express PCI x4/x2/x1 PCI PCI Express x1 DMA x4/x2/x1 1 Max Value Unit –0 –0 –0 –0 Freescale Semiconductor Notes — — — — ...

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... Characteristic Core supply voltage PLL supply voltage Core power supply for SerDes transceivers Pad power supply for SerDes transceivers DDR and DDR2 DRAM I/O voltage MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor 1 (continued) Symbol Max Value GV –0.3 to 2.75 DD – ...

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... V ± 125 mV TV 3.3 V ± 165 mV DD 2.5 V ± 125 mV OV 3.3 V ± 165 3.3 V ± 165 2.5 V ± 125 mV 1.8 V ± GND GND REF DD LV GND GND GND GND ° 105 j and not necessarily the voltage Freescale Semiconductor Notes — ...

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... I/O supply voltage. OV appropriate LVCMOS type specifications. The DDR2 SDRAM interface uses a single-ended differential receiver referenced the externally supplied MV the SSTL2 electrical signaling standard. MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor + 20 GND Not to Exceed 10% ...

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... Table 3. Output Drive Capability Programmable Output Impedance (Ω (default) 45 (default) 125 25 42 (default (half strength mode 150 , Supply Notes Voltage 2.5 V — 1.8 V — 2.5/3.3 V — 3.3 V — 3.3 V — required. If there is DD core supply, the I/Os DD Freescale Semiconductor ...

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... Section 4.3, “eTSEC Gigabit Reference Clock Timing” • Section 4.4, “Platform to FIFO Restrictions” • Section 4.5, “Other Input Clocks” MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor Table 4. Table 4. MPC8544ECore Power Dissipation Platform Frequency V DD ...

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... Table 2. Table 5. Typical Max Unit — 133 MHz — 30.3 ns 1.0 2.1 ns — — ±150 ps and Section 19.3, “e500 Core PLL Ratio,” Table 5 Min Max Unit 20 60 kHz 0 1.0 % Freescale Semiconductor Notes 1 — 2 — for ratio Notes — 1 ...

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... FIFO TX/RX clock frequency ≤ platform clock frequency ÷ 3.2 For example, if the platform frequency is 533 MHz, the FIFO Tx/Rx clock frequency should be no more than 167 MHz. MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor , and minimum clock low time is 2 × t CCB Symbol ...

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... Table 9. PLL Lock Times Min — — — (typ) = 2.5 V and DDR2 SDRAM Max Unit Notes μs — — — SYSCLKs 1 μs — — — SYSCLKs 1 — SYSCLKs 1 5 SYSCLKs 1 Max Unit Notes μs 100 — μs 50 — μs 50 — (typ Freescale Semiconductor ...

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... DDR SDRAM component(s) when GV (typ Table 12. DDR SDRAM DC Electrical Characteristics for GV Parameter/Condition I/O supply voltage I/O reference voltage I/O termination voltage Input high voltage Input low voltage MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor . Symbol Min GV 1.71 DD 0.49 × REF ...

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... Max Unit μA 50 — mA — (typ Min Max Unit — 0 /2, V (peak-to-peak) = 0.2 V. OUT DD OUT REF Min Max Unit μA — 500 (typ Max Unit MV – 0.25 V REF + 0.25 — V Freescale Semiconductor Notes 4 — — Notes 1 1 Notes 1 Notes — — ...

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... Figure CISKEW 3. Maximum DDR1 frequency is 400 MHz. Figure 3 shows the DDR SDRAM input timing diagram. MCK[n] MCK[n] MDQS[n] MDQ[x] Figure 3. DDR SDRAM Input Timing Diagram (t MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor Symbol Min V — 0.31 IH REF Symbol ...

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... MHz 900 t 0.75 x tMCK DDKHMP Max Unit Notes — 7 — — — 7 — — — — — 7 — — — — — 7 — — — — 0 — 7 — — — — — 7 — — — — — Freescale Semiconductor ...

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... Figure 4 shows the DDR SDRAM output timing for the MCK to MDQS skew measurement (t MCK[n] MCK[n] MDQS MDQS MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor 1 Symbol Min t 0.4 x tMCK DDKHME (first two letters of functional block)(signal)(state)(reference)(state) for outputs ...

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... MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev MCK DDKHAS DDKHCS DDKHAX DDKHCX NOOP t DDKHMP t DDKHMH t DDKHDS DDKHDX = 50 Ω Figure 6. DDR AC Test Load Symbol –2 mA DDKHME t DDKLDS t DDKLDX Ω Min Max Unit 0 –0.3 0.8 V μA — ±5 2.4 — V Freescale Semiconductor Notes — — 1 — ...

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... RMII Consortium RMII Specification Version 1.2 (3/20/1998). The SGMII interfaces follow the Serial Gigabit Media-Independent Interface (SGMII) Specification Version 1.8. The electrical MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor Enhanced Three-Speed Ethernet (eTSEC), MII Management Symbol ...

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... Table 1 and Table 2. Min Max Unit 2.375 2.625 V 2.0 — V — 0.4 V 1.70 — V — 0.7 V μA — ±15 Table 1 and Table 2. Freescale Semiconductor Notes 1, 2 — — — — Notes 1, 2 — — — — ...

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... DD_SRDS2 Output high voltage V Output low voltage Output ringing V MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor Enhanced Three-Speed Ethernet (eTSEC), MII Management 7, where C is the external (on board) AC-coupled capacitor. Each output TX Figure as long as such termination does not violate 8 ...

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... TX-DIFFp amplitude—power up default); DD-DIFF-p common mode offset DD_SRDS2-Typ Freescale Semiconductor Notes Equalization setting: 1.0x Equalization Equalization setting: 1.2x Equalization Equalization setting: 1.5x Equalization Equalization setting: 2. — — — — — ...

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... Figure 8. SGMII Transmitter DC Measurement Circuit Table 25 shows the DC receiver electrical characteristics. Table 25. DC Receiver Electrical Characteristics Parameter Supply Voltage DC input voltage range MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor Enhanced Three-Speed Ethernet (eTSEC), MII Management SD2_TXn 50 Ω SD_RXm Ω ...

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... Notes — 1200 mV — — 100 mV — 175 — 100 mV Ω — 120 Ω — 35 — xcorevss V Typ Max Unit Notes — 0.17 UI p-p — 0.35 UI p-p 800 800.08 ps — 120 ps — 120 ps Freescale Semiconductor — — 6 — — 2 — — ...

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... The external AC coupling capacitor is required. It’s recommended to be placed near the device transmitter outputs. Vrx_diffpp_max/2 Vrx_diffpp_min/2 –Vrx_diffpp_min/2 –Vrx_diffpp_max/2 MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor Enhanced Three-Speed Ethernet (eTSEC), MII Management Figure 9 shows the SGMII receiver input compliance mask Symbol Min J 0 ...

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... MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev Pin Pin Silicon + Package Ω Pin Table 28 and Symbol Min t — FIT t 45 FITH t — FITJ t — FITR Ω Table 29. Typ Max Unit Notes 8.0 — — 250 ps — 0.75 ns Freescale Semiconductor — — — — ...

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... TX_EN TX_ER Figure 11. FIFO Transmit AC Timing Diagram RX_CLK t FIRH RXD[7:0] RX_DV RX_ER Figure 12. FIFO Receive AC Timing Diagram MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor Enhanced Three-Speed Ethernet (eTSEC), MII Management Symbol Min t — FITF t 0.5 FITDX Symbol Min t — ...

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... GMII(G) transmit (TX) clock. For rise and fall times, the latter convention t GTX t t GTXH GTXF t GTKHDX t GTKHDV Min Typ Max Unit — 8.0 — ns 0.2 — 5.0 ns — — 1.0 ns — — 1.0 ns symbolizes GMII transmit timing GTKHDV t GTXR Freescale Semiconductor Notes — 2 — — for inputs clock GTX ...

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... GMII receive AC timing diagram. RX_CLK RXD[7:0] RX_DV RX_ER 8.6 MII AC Timing Specifications This section describes the MII transmit and receive AC timing specifications. MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor Enhanced Three-Speed Ethernet (eTSEC), MII Management 1 Symbol t GRX t /t GRXH ...

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... MRX MRXH MRX Typ Max Unit 400 — — ns — — 4.0 ns — 4.0 ns symbolizes MII transmit MTKHDX t MTXR Typ Max Unit 400 — — ns — Freescale Semiconductor Notes — — — — — — for Notes — — — ...

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... MII receive AC timing diagram. RX_CLK RXD[3:0] RX_DV RX_ER 8.7 TBI AC Timing Specifications This section describes the TBI transmit and receive AC timing specifications. MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor Enhanced Three-Speed Ethernet (eTSEC), MII Management 1 Symbol Min t 10.0 MRDVKH t 10 ...

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... Min t — TRX t 7.5 SKTRX Typ Max Unit 8.0 — ns — 5.0 ns — 1.0 ns — 1.0 ns symbolizes the TBI TTKHDV TTX t TTXR t TTKHDX Typ Max Unit 16.0 — ns — 8.5 ns Freescale Semiconductor Notes — 2 — — for (K) going Notes — — ...

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... TSECn_RX_CLK pin (no receive clock is used on TSECn_TX_CLK in this mode, whereas for the dual-clock mode this is the PMA1 receive clock). The 125-MHz transmit clock is applied on the TSEC_GTX_CLK125 pin in all TBI modes. MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor Enhanced Three-Speed Ethernet (eTSEC), MII Management 1 Symbol ...

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... RGTR Table 36. Typ Max Unit Notes 8.0 8.5 ns — — — 250 ps — — 1.0 ns — — 1.0 ns — — — ns — — — ns — t TRRR t TRRF Typ Max Unit Notes 0 500 ps 5 — 2 8.0 8 — 0.75 ns — Freescale Semiconductor ...

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... PHY) GTX_CLK (At Receiver) RXD[8:5][3:0] RXD[7:4][3:0] RX_CTL RX_CLK (At PHY) Figure 22. RGMII and RTBI AC Timing and Multiplexing Diagrams MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor Enhanced Three-Speed Ethernet (eTSEC), MII Management of 2.5 V ± 5 Symbol Min t — RGTF represents the TBI (T) receive (RX) clock ...

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... MII(M) transmit (TX) clock. For rise and fall times, the latter convention is t RMT t t RMTF RMTH t RMTDX Typ Max Unit 20.0 25 — — 250 ps 1.0 — 2.0 ns 1.0 — 2.0 ns 1.0 — 10.0 ns symbolizes MII transmit MTKHDX t RMTR Freescale Semiconductor Notes — — — — — — for ...

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... AC test load for eTSEC. Output Figure 25 shows the RMII receive AC timing diagram. REF_CLK RXD[1:0] CRS_DV RX_ER MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor Enhanced Three-Speed Ethernet (eTSEC), MII Management of 3.3 V ± 5%.or 2.5 V ± 5 Symbol Min t 15.0 ...

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... Table 1 and Table 2. Typ Max Unit 2.5 — MHz 400 — ns — — ns — (16 × plb_clk — — ns — — ns — Freescale Semiconductor Notes — — — — — 1 — Notes 2 — — — — — ...

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... Figure 26 shows the MII management AC timing diagram. MDC MDIO (Input) MDIO (Output) Figure 26. MII Management Interface Timing Diagram MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor Ethernet Management Interface Electrical Characteristics is 3.3 V ± 5 Symbol Min t — MDHF (first two letters of functional block)(signal)(state)(reference)(state) for outputs ...

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... Table 2. Min Max Unit 1. 0 –0.3 0.7 V μA — ±15 2.0 — V — 0.4 V and Table 2. Min Max Unit 1 0 –0.3 0.6 V μA — ±15 Freescale Semiconductor Notes — — 1 — — Notes — — 1 — — Notes — — 1 ...

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... Output hold from local bus clock (except LAD/LDP and LALE) Output hold from local bus clock for LAD/LDP Local bus clock to output high Impedance (except LAD/LDP and LALE) MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor Symbol Min Max V 1.35 — ...

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... LBOTOT = 2 2.5 V) —PLL Enabled DD Min Max Unit 7 — 150 ps 2.4 — ns 1.8 — ns 1.1 — ns 1.1 — ns 1.5 — ns — 2.8 ns — 2.8 ns — 2.8 ns — 2.8 ns 0.8 — ns 0.8 — ns — 2.6 ns Freescale Semiconductor Notes 5 for is Notes 2 — — ...

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... Output hold from local bus clock (except LAD/LDP and LALE) Output hold from local bus clock for LAD/LDP Local bus clock to output high Impedance (except LAD/LDP and LALE) MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor DD 1 Symbol t LBKHOZ2 (first two letters of functional block)(signal)(state)(reference)(state) for outputs ...

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... LSYNC_IN for PLL enabled or internal local bus clock for PLL = 50 Ω Figure 27. Local Bus AC Test Load = 1.8 V DC) (continued) DD Min Max Unit — 2.6 ns symbolizes local bus LBIXKH1 clock reference (K) goes high (H), in this case for LBOTOT Ω L Freescale Semiconductor Notes 5 for is ...

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... Input hold from local bus clock (except LUPWAIT) LUPWAIT input hold from local bus clock LALE output transition to LAD/LDP output transition (LATCH hold time) Local bus clock to output valid (except LAD/LDP and LALE) MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor t LBIVKH1 t LBIVKH2 t ...

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... PLL bypass mode to 0.4 × BV Min Max Unit — 1.6 ns — 1.6 ns –4.1 — ns –4.1 — ns — 1.4 ns — 1.4 ns symbolizes local bus LBIXKH1 clock reference (K) goes high (H), in this case clock reference ( high (H), with respect of the signal DD Freescale Semiconductor Notes for ...

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... In PLL bypass mode, LCLK[n] is the inverted version of the internal clock with the delay of t edge of the internal clock and are captured at falling edge of the internal clock withe the exception of LGTA/LUPWAIT (which is captured on the rising edge of the internal clock). MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor t LBKHKT t LBKLOV1 t ...

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... LUPWAIT Input Signals: LAD[0:31]/LDP[0:3] UPM Mode Output Signals: LCS[0:7]/LBS[0:3]/LGPL[0:5] Figure 30. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV (PLL Enabled) MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev LBKHOV1 LBKHOZ1 t LBIVKH2 t LBIVKH1 t t LBKHOV1 LBKHOZ1 t LBIXKH2 t LBIXKH1 Freescale Semiconductor ...

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... UPM Mode Input Signal: LUPWAIT Input Signals: LAD[0:31]/LDP[0:3] UPM Mode Output Signals: LCS[0:7]/LBS[0:3]/LGPL[0:5] Figure 31. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV (PLL Bypass Mode) MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor t t LBKLOX1 LBKLOV1 t LBIVKH1 Local Bus ...

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... LUPWAIT Input Signals: LAD[0:31]/LDP[0:3] UPM Mode Output Signals: LCS[0:7]/LBS[0:3]/LGPL[0:5] Figure 32. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV (PLL Enabled) MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev LBKHOV1 LBKHOZ1 t LBIVKH2 t LBIVKH1 t t LBKHOV1 LBKHOZ1 t LBIXKH2 t LBIXKH1 Freescale Semiconductor ...

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... Figure 33. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV (PLL Bypass Mode) 11 Programmable Interrupt Controller In IRQ edge trigger mode, when an external interrupt signal is asserted (according to the programmed polarity), it must remain the assertion for at least 3 system clocks (SYSCLK periods). MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor t t LBKLOX1 LBKLOV1 ...

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... Max Unit 0 –0.3 0.8 V μA — ±5 2.4 — V — 0.4 V Figure 34 through Figure 37. 1 Min Max Unit 0 33.3 MHz 30 — — — — 0 — — 25 — — 4 — Freescale Semiconductor Notes — — 1 — — Notes — — — — ...

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... Figure 35 provides the JTAG clock input timing diagram. JTAG External Clock Figure 35. JTAG Clock Input Timing Diagram Figure 36 provides the TRST timing diagram. TRST MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor Table 3). 2 Symbol Boundary-scan data t JTKLDZ TDO ...

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... C DC Electrical Characteristics of 3.3 V ± 5%. DD Symbol 0.7 × I2KHKL switched off JTDXKH Input Data Valid Output Data Valid 2 C interfaces of the MPC8544E. Min Max Unit 0.3 × OV –0 0.2 × μA –10 10 — Freescale Semiconductor Notes — — — ...

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... SCL. 3. The maximum t has only to be met if the device does not stretch the LOW period (t I2DXKL capacitance of one bus line in pF. B MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor 2 C interfaces. 2 Table 52 Electrical Specifications Table 51). ...

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... I2SVKH t t I2DXKL, I2OXKL Sr 2 Figure 39 Bus AC Timing Diagram Symbol – symbol referenced Ω I2CF t I2CR t I2PVKH P S Min Max Unit 0 –0.3 0.8 V μA — ±5 2.4 — V — 0.4 V Table 1 and Table 2. Freescale Semiconductor Notes — — 1 — — ...

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... Notes: 1. Ranges listed do not meet the full range of the DC specifications of the PCI 2.2 Local Bus Specifications. 2. Note that the symbol this case, represents the OV IN MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor = 50 Ω Figure 40. GPIO AC Test Load Symbol ...

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... Max Unit — 7.4 ns 2.0 — ns — 3.7 — ns 0.5 — × t — clocks SYS — clocks 0.6 2.1 ns 0.6 2.1 ns symbolizes PCI timing PCIVKH , reference (K) SYS of the signal in question for DD Section 19, “Clocking.” Ω Freescale Semiconductor Notes — — for ...

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... For illustration purpose, only one SerDes lane is used for description. The figure shows waveform for either a transmitter output (SDn_TX and SDn_TX receiver input (SDn_RX and SDn_RX). Each signal swings between A Volts and B Volts where A > B. MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor t PCIVKH CLK ...

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... SDn_RX. DIFFp = |A – B| Volts. DIFFp DIFFp |(A – B)| Volts, which is twice of differential swing in DIFFp = 2*|V |. TX-DIFFp-p OD Figure defined as the difference of OD The V value can be either positive defined as the difference of the ID The V value can be either positive example for differential waveform. cm_out Freescale Semiconductor = ...

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... Figure 45. Each differential clock input (SDn_REF_CLK or SDn_REF_CLK) has a 50-Ω termination to SGND_SRDSn (xcorevss) followed by on-chip AC-coupling. — The external reference clock driver must be able to drive this termination. MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor Differential Swing Differential Peak Voltage, V ...

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... In other words, each signal wire of the differential pair must have a single-ended swing less than 800 mV and greater than 200 mV. This requirement is the same for both external DC-coupled or AC-coupled connection. MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev Ω Input Amp 50 Ω Freescale Semiconductor ...

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... Input Amplitude or Differential Peak < 800 mV SDn_REF_CLK SDn_REF_CLK Figure 47. Differential Reference Clock Input DC Requirements (External AC-Coupled) MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor High-Speed Serial Interfaces (HSSI) Section 16.2.1, “SerDes Reference Figure 47 shows the SerDes reference clock Figure 48 Vmax < ...

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... They might also vary from one vendor to the other. Therefore, Freescale Semiconductor can neither provide the optimal clock driver reference circuits, nor guarantee the correctness of the following clock driver connection reference circuits. The system designer is recommended ...

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... Since LVPECL driver’s DC levels (both common mode voltages and output swing) are incompatible with MPC8544E SerDes reference clock input’s DC requirement, AC-coupling has to be used. MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor SDn_REF_CLK 100 Ω differential PWB trace ...

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... PWB trace 10nF R2 SDn_REF_CLK Total 50 Ω. Assume clock driver’s output impedance is about 16 Ω. SDn_REF_CLK 100 Ω differential PWB trace SDn_REF_CLK Ω 50 MPC8544E 50 Ω SerDes Refer. CLK Receiver 50 Ω MPC8544E 50 Ω SerDes Refer. CLK Receiver 50 Ω Freescale Semiconductor ...

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... Rise Edge Rage V = +200 –200 mV IL SDn_REF_CLK minus SDn_REF_CLK Figure 53. Differential Measurement Points for Rise and Fall Time MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor Symbol Min Rise Edge Rate Fall Edge Rate V +200 Rise-Fall Matching Figure 53. ...

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... MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev SDn_REF_CLK V + 100 mV CROSS MEDIAN V CROSS MEDIAN V – 100 mV CROSS MEDIAN SDn_REF_CLK SD1_TXn or SD1_RXn or SD2_TXn SD2_RXn SD1_TXn or SD1_RXn or SD2_TXn SD2_RXn T T FALL RISE 50 Ω Receiver 50 Ω Freescale Semiconductor ...

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... The following is a summary of the specifications for the physical layer of PCI Express on this device. For further details as well as the specifications of the transport and data link layer please refer to the PCI Express Base Specification. Rev. 1.0a. MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor Min Typ Max Units — ...

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... T TX-MAX-JITTER TX-EYE TX-DIFFp-p = RMS(|V – TXD+ |/2 – TX-CM- – (avg) TX-D+ |/2 – V TX-CM-DC (during LO) TX-CM-Idle-DC |<= 100 – (avg) TX-D+ |/2 [LO – (avg) TX-D+ |/2 [Electrical Idle] – < TX-CM-DC-D+ TX-CM-DC-D– (avg) TX- (avg) TX-D– – V TX-IDLE-D+ TX-IDLE-D– Freescale Semiconductor | ...

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... Transmitter DC TX-DC impedance L Lane-to-lane output TX-SKEW skew C AC coupling capacitor TX MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor Min Nom Max Unit — — 600 mV The total amount of voltage change that a transmitter can apply to sense whether a low impedance receiver is present. See Note 6 ...

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... See Note 7. Figure 58 and measured over Figure 56.) = 0.30 UI for the TX-JITTER-MAX median is less than half of the total Figure 58.) Note that the series capacitors Figure 58 for both V and V TX-D+ TX-D– Freescale Semiconductor . ...

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... Parameter UI Unit interval V Differential peak-to- RX-DIFFp-p peak input voltage T Minimum receiver RX-EYE eye width MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor [Transition Bit 800 mV TX-DIFFp-p-MIN [De-Emphasized Bit] 566 mV (3 dB) >= V >= 505 mV (4 dB) TX-DIFFp-p-MIN 0. – 0 TX-TOTAL-MAX [Transition Bit] ...

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... Measured at the package pins of the receiver. — — unexpected electrical idle (V < longer than T signal an unexpected idle condition. Comments RX-DIFFp-p | ÷ 2 – – V RXD+ RXD– – V |/2 (avg) RX-D+ RX-D– × |V – V RX-D+ RX-D– RX-DIFFp-p ) must be recognized RX-IDLE-DET-DIFFp-p RX-IDLE-DET-DIFF-ENTERING Freescale Semiconductor | to ...

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... RX package and silicon. The RX eye diagram must be aligned in time using the jitter median to locate the center of the eye diagram. MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor Min Nom Max Units — ...

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... Figure 58. Compliance Test/Measurement Load MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev NOTE Figure 57). Note that the series capacitors, CTX, are V > 175 mV RX-DIFFp-p-MIN 0 RX-EYE-MIN NOTE Pin Pin Silicon + Package Ω Pin RX-DIFF (D+ D– Crossing Point) Figure 58 Ω Freescale Semiconductor ...

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... The package parameters for flip chip plastic ball grid array (FC-PBGA) are provided in Package outline Interconnects Ball pitch Ball diameter (typical) Solder ball (Pb-free) Note: 1. (FC-PBGA) without a lid. MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor Table 61. Package Parameters 1 Parameter PBGA 29 mm × 783 ...

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... Capacitors may not be present on all parts. Care must be taken not to short exposed metal capacitor pads. 7. All dimensions are symmetric across the package center lines, unless dimensioned otherwise. Figure 59. Mechanical Dimensions and Bottom Surface Nomenclature MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev the MPC8544E FC-PBGA without a Lid Freescale Semiconductor ...

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... AF9, AG10, AH10, AD6 PCI1_REQ0 AB8 PCI1_CLK AH26 PCI1_DEVSEL AC13 PCI1_FRAME AD12 PCI1_IDSEL AG6 MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor NOTE NOTE Table 62 Table 62. MPC8544E Pinout Listing Package Pin Number PCI Package Description for more details. Power Pin Type Notes ...

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... Package Pin Number DDR SDRAM Memory Interface Local Bus Controller Interface Power Pin Type Notes Supply I/O GV — DD I/O GV — I/O GV — DD I/O GV — — — — — — — — — — — — — Freescale Semiconductor 1 ...

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... AG22, AF17, AD21, AF19, AG17, AF16, AC23, AC22 IRQ[8] AC19 IRQ[9]/DMA_DREQ3 AG20 IRQ[10]/DMA_DACK3 AE27 IRQ[11]/DMA_DDONE3 AE24 IRQ_OUT AD14 MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor Package Pin Number DMA Programmable Interrupt Controller Package Description Power Pin Type Notes Supply ...

Page 86

... MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev Package Pin Number Ethernet Management Interface Gigabit Reference Clock DUART Power Pin Type Notes Supply I/O OV — — — — — — — — — — — — — — — — — — DD Freescale Semiconductor ...

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... AA2 SD2_TX[0] AA21 SD2_TX[2] AC4 SD2_TX[3] AA5 SD2_TX[0] AA20 SD2_TX[2] AB4 SD2_TX[3] Y5 SD2_PLL_TPD AG3 SD2_REF_CLK AE2 MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor Package Pin Number interface SerDes 1 SerDes 2 Package Description Power Pin Type Notes Supply I OV — — ...

Page 88

... MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev Package Pin Number General-Purpose Output General-Purpose Input System Control Debug Clock JTAG Power Pin Type Notes Supply I XV — DD — — — — — — — — — — — — 15 15 — — — Freescale Semiconductor 5 ...

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... G11, H5, H12, E22, F15, J10, K3, K12, K14, H14, D20, E11, M1 L23, J18, J19, F20, F23, H26, J21, J23 DD MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor Package Pin Number DFT Thermal Management Power Management Power and Ground Signals Power for DDR1 local bus (1 ...

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... SerDes PLL — GND Power for local — bus PLL (1.0 V) Power for PCI — PLL (1.0 V) — PLL (1.0 V) Power for CCB — PLL (1.0 V) Freescale Semiconductor Notes — — — — — — — — — — — ...

Page 91

... Thus, no external pull-down resistor is needed for selecting the default configuration value. 5. Treat these pins as no connects (NC) unless using debug address functionality. MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor Package Pin Number Analog Signals No Connect Pins ...

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... MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev Package Pin Number Section 19.3, “e500 Core PLL Ratio.” /GND planes internally and may be used by the core power supply to improve tracking Power Pin Type Notes Supply for normal machine operation. DD through an 18.2-Ω precision DD Freescale Semiconductor ...

Page 93

... The frequency of the CCB is set using the following reset signals (see • SYSCLK input signal • Binary value on LA[28:31] at power up MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor Maximum Processor Core Frequency 800 MHz 1000 MHz Max Min ...

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... Table 66. e500 Core to CCB Clock Ratio Binary Value of LBCTL, LALE, LGPL2 Signals 4:1 100 Reserved 101 Reserved 110 3:2 111 CCB:SYSCLK Ratio 8:1 9:1 10:1 Reserved 12:1 Reserved Reserved Reserved Table 66. e500 core:CCB Clock Ratio 2:1 5:2 3:1 7:2 Freescale Semiconductor ...

Page 95

... Table 68. Frequency Options of SYSCLK with Respect to Memory Bus Speeds CCB to SYSCLK Ratio 33. 333 12 400 16 533 MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor Table 67. SEC Frequency Ratio Value (Binary SYSCLK (MHz) 41.66 66.66 83 Platform /CCB Frequency (MHz) — 333 333 415 400 500 333 ...

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... JEDEC Board Single layer board (1s) Four layer board (2s2p) Single layer board (1s) Four layer board (2s2p) — — Section 4.4, 1 (MHz) 126 94 Symbol Value Unit °C θJA °C θJA °C θJA °C θJA °C θJB °C/W R <0.1 θJC Freescale Semiconductor Notes ...

Page 97

... Table 72 shows the MPC8544E thermal model. Conductivity Silicon Bump/Underfill (7.6 × 8.4 × 0.070 mm) Collapsed Thermal Resistance MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor Air Flow Natural convection 1 m/s Natural convection 1 m/s Natural convection 1 m/s Natural convection 1 m/s Figure 59 Table 72 ...

Page 98

... The user will need to determine the optimal grid for their specific case. MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev Value Solder and Air (29 × 29 × 0.58 mm) 0.034 0.034 12.1 Die Substrate Solder/Air Units W/m•K A Freescale Semiconductor ...

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... Access Road #27. Norwood, MA02062 Internet: www.qats.com Alpha Novatech408-567-8082 473 Sapena Ct. #12 Santa Clara, CA 95054 Internet: www.alphanovatech.com MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor Section 20.3.4, “Temperature Diode,” FC-PBGA Package Heat Sink Heat Sink Clip Adhesive or Die Thermal ...

Page 100

... Internal Package Conduction Resistance For the packaging technology, shown in are as follows: • The die junction-to-case thermal resistance • The die junction-to-board thermal resistance MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 100 Table 70, the intrinsic internal conduction thermal resistance paths Freescale Semiconductor ...

Page 101

... As shown, the performance of these thermal interface materials improves with increasing contact pressure. The use of thermal grease significantly reduces the interface thermal resistance. The bare joint results in a thermal resistance approximately six times greater than the thermal grease joint. MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor Radiation Convection Heat Sink ...

Page 102

... Shin-Etsu MicroSi, Inc.888-642-7674 10028 S. 51st St. Phoenix, AZ 85044 Internet: www.microsi.com The Bergquist Company800-347-4572 th 18930 West 78 St. MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 102 Silicone Sheet (0.006 in.) Bare Joint Floroether Oil Sheet (0.007 in.) Graphite/Oil Sheet (0.005 in.) Synthetic Grease Contact Pressure (psi Freescale Semiconductor ...

Page 103

... Assuming an air velocity of 1 m/s, we have an effective θ = 30° + 5°C + (0.1°C/W + 1.0°C/W + 5°C/W) × resulting in a die-junction temperature of approximately 66, which is well within the maximum operating temperature of the component. MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor + θ + θ ) × INT SA ...

Page 104

... The ideality factor is defined as the deviation from the ideal diode equation nKT – Another useful equation is – MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 104 Thermalloy #2328B Pin-fin Heat Sink (25 × 28 × 15 mm) 0.5 1 1.5 2 Figure 64. Approach Air Velocity (m/ 2.5 3 3.5 Freescale Semiconductor ...

Page 105

... The PCI PLL generates the clocking for the PCI bus. • The local bus PLL generates the clock for the local bus. • There are two PLLs for the SerDes block. MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor is flowing H is flowing L –19 C) – ...

Page 106

... Ω 2.2 µF 2.2 µF Low ESL Surface Mount Capacitors GND 1.0 Ω 2.2 µF 2.2 µF GND _SRDS, respectively). The AV DD Figure 65, one to each of the pin being supplied to minimize _SRDS DD 0.003 µF Freescale Semiconductor ...

Page 107

... Third, between the device and any SerDes voltage regulator there should be a 10-µF, low equivalent series resistance (ESR) SMT tantalum chip capacitor and a 100-µF, low ESR SMT tantalum chip capacitor. This should be done for all SerDes supplies. MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor . DD DD ...

Page 108

... MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 108 , C). To measure Z or GND. Then, the value of each resistor (see Figure 67). The output impedance is the average of two and (Table 62) for more for the single-ended drivers, 0 /2. R then becomes the DD P Freescale Semiconductor , ...

Page 109

... The default value for all configuration bits treated this way has MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor and R are designed to be close to each other in value. Then, ...

Page 110

... IC). Regardless of the numbering, the signal placement recommended in all known emulators. MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 110 Figure 69 allows the COP port to Figure 68, for connection to the target system, and is Figure 68 is common to Freescale Semiconductor ...

Page 111

... JTAG interface may need to be wired onto the system in future debug situations. • No pull-up/pull-down is required for TDI, TMS, or TDO. Figure 68 shows the COP connector physical pinout. COP_RUN/STOP COP_SRESET COP_HRESET COP_CHKSTP_OUT MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor COP_TDO NC COP_TDI 3 4 COP_TRST ...

Page 112

... COP_TRST 10 Ω 2 COP_VDD_SENSE NC COP_CHKSTP_OUT 10 kΩ 3 COP_CHKSTP_IN COP_TMS COP_TDO COP_TDI COP_TCK Figure 69. JTAG Interface Connection kΩ 6 SRESET 1 10 kΩ HRESET 10 kΩ 10 kΩ 10 kΩ 10 kΩ 1 TRST CKSTP_OUT 10 kΩ CKSTP_IN TMS TDO TDI TCK 10 kΩ Freescale Semiconductor ...

Page 113

... All PCI control pins can be grouped together and tied to OV • optional to disable PCI block through DEVDISR register after POR reset. MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor System Design Information through a single 10-kΩ resistor. DD 113 ...

Page 114

... MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 114 Power-On Hours Part-time/ Full-Time PC's, consumer electronics, office automation, SOHO networking, portable telecom products, PDAs, etc. Typically Full-Time Installed telecom equipment, work stations, servers, warehouse equipment, etc. through a single 10-kΩ resistor. DD Table 74 provides a Example of Typical Applications Freescale Semiconductor ...

Page 115

... MMMMM is the 5-digit mask number. ATWLYYWW is the traceability code. CCCCC is the country of assembly. This space is left blank if parts are assembled in the United States. Figure 70. Part Marking for FC-PBGA Device MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor Table 75. Device Nomenclature ...

Page 116

... Section 22, “Device Nomenclature,” with regards to Commercial Tier. Table 18 DDR SDRAM Output AC Timing Specifications tMCK Max value Section 16, “High-Speed Serial Interfaces (HSSI) Mechanical Dimensions Table 48 Local Bus General Timing Parameters—PLL Bypassed to show max local bus frequency Freescale Semiconductor ...

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... Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer ...