MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 261

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

6.13.2
Freescale Semiconductor
Reset
Reset
38–39 DAC2ER Data address compare 2 effective/real mode
40–41 DAC12M Data address compare 1/2 mode
42–63
SPR: 304
Bits
W w1c
W w1c
R
R RET
IDE
32
48
0
Name
—
UDE
w1c
Debug Status Register (DBSR)
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
33
49
0
00 DAC2 debug events are based on effective addresses.
01 Reserved on the e500
10 DAC2 debug events are based on effective addresses and can occur only if MSR[DS] = 0.
11 DAC2 debug events are based on effective addresses and can occur only if MSR[DS] = 1.
00 Exact address compare. DAC1 debug events can occur only if the address of the data storage access
01 Address bit match. DAC1 and DAC2 debug events can occur only if the address of the data storage
10 Inclusive address range compare. DAC1 and DAC2 debug events can occur only if the address of the
11 Exclusive address range compare. DAC1 and DAC2 debug events can occur only if the address of the
Reserved, should be cleared.
If DAC1US ≠ DAC2US or DAC1ER ≠ DAC2ER, results are boundedly undefined.
undefined
is equal to the value specified in DAC1. DAC2 debug events can occur only if the address of the data
storage access is equal to the value specified in DAC2.
access, ANDed with the contents of DAC2 are equal to the contents of DAC1, also ANDed with the
contents of DAC2.
If DAC1US ≠ DAC2US or DAC1ER ≠ DAC2ER, results are boundedly undefined.
data storage access is greater than or equal to the value specified in DAC1 and less than the value
specified in DAC2.
If DAC1US ≠ DAC2US or DAC1ER ≠ DAC2ER, results are boundedly undefined.
data storage access is less than the value specified in DAC1 or is greater than or equal to the value
specified in DAC2.
34
MRR
w1c
35
Table 6-37. DBCR2 Field Descriptions (continued)
ICMP BRT
w1c
Figure 6-53. Debug Status Register (DBSR)
36
0
w1c
37
0
IRPT TRAP IAC1 IAC2
w1c
38
0
w1c
39
0
All zeros
w1c
Description
40
0
—
w1c
41
0
42
0
—
43
0
DAC1
w1c
44
R
0
DAC1W
Access: Supervisor w1c
w1c
45
0
Core Register Summary
DAC2
w1c
46
R
0
DAC2W
w1c
47
63
0
6-43