MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 22

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Paragraph
Number
12.5.1.3
12.5.1.4
12.5.1.5
12.5.1.6
12.5.2
12.5.2.1
12.5.2.2
12.5.2.3
12.6
12.6.1
12.6.1.1
12.6.1.2
12.6.2
12.6.2.1
12.6.2.2
12.6.2.3
12.6.2.4
12.6.3
12.6.4
12.6.5
12.6.5.1
12.6.5.2
12.6.5.3
12.6.5.4
12.6.5.5
12.6.5.6
12.6.5.7
12.7
13.1
13.1.1
13.1.2
13.2
13.2.1
13.2.2
13.3
13.3.1
13.3.1.1
xxii
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Security Controller..................................................................................................... 12-104
Power-Saving Mode................................................................................................... 12-115
Overview........................................................................................................................ 13-1
External Signal Descriptions ......................................................................................... 13-3
Memory Map/Register Definition ................................................................................. 13-4
Channel Interrupts.................................................................................................. 12-103
Assignment of EUs to Channels ............................................................................ 12-104
Bus Transfers ......................................................................................................... 12-105
Snooping by Caches............................................................................................... 12-108
Controller Interrupts .............................................................................................. 12-108
Controller Registers ............................................................................................... 12-109
Features...................................................................................................................... 13-1
Modes of Operation ................................................................................................... 13-2
Signal Overview ........................................................................................................ 13-3
Detailed Signal Descriptions ..................................................................................... 13-3
Register Descriptions................................................................................................. 13-6
Crypto-Channel Current Descriptor Pointer Registers 1–4 (CCDPRn) ............ 12-100
Fetch FIFO Address Registers 1–4 (FFn).......................................................... 12-101
Crypto-Channel 1–4 Descriptor Buffers [0–7] (DBn[0–7]) .............................. 12-102
Link Table Buffer Registers (Scatter or Gather)—LTB0–3 .............................. 12-102
Channel Done Interrupt ..................................................................................... 12-103
Channel Error Interrupt...................................................................................... 12-103
Channel Reset .................................................................................................... 12-103
Channel Priority Arbitration .............................................................................. 12-105
Channel Round-Robin Arbitration .................................................................... 12-105
Arbitration for Use of the Controller and Buses................................................ 12-106
System Bus Master Reads ................................................................................. 12-107
System Bus Master Writes................................................................................. 12-107
System Bus Slave Transactions (Reads and Writes) ......................................... 12-107
EU Assignment Status Register (EUASR) ........................................................ 12-109
Interrupt Mask Register (IMR).......................................................................... 12-110
Interrupt Status Register (ISR) ...........................................................................12-111
Interrupt Clear Register (ICR) ........................................................................... 12-112
ID Register......................................................................................................... 12-113
IP Block Revision Register................................................................................ 12-113
Master Control Register (MCR) ........................................................................ 12-114
Receiver Buffer Registers (URBR0, URBR1) (ULCR[DLAB] = 0) .................... 13-6
Contents
Chapter 13
DUART
Title
Freescale Semiconductor
Number
Page