MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 1035

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Figure 17-49
Figure 17-50
17.4.2.7.2
This section describes PCI single-beat write transactions, and PCI burst write transactions. A PCI write
transaction starts with the address phase, occurring when an initiator asserts PCI_FRAME. A write
transaction is similar to a read transaction except no turnaround cycle is needed following the address
phase because the initiator provides both address and data. The data phases are the same for both read and
write transactions. Although not shown in the figures, the initiator must drive the PCI_C/BE[3:0] signals,
even if the initiator is not ready to provide valid data (PCI_IRDY negated).
Freescale Semiconductor
PCI_DEVSEL
PCI_DEVSEL
PCI_FRAME
PCI_FRAME
PCI_TRDY
PCI_TRDY
PCI_C/BE
PCI_IRDY
PCI_C/BE
PCI_IRDY
illustrates a PCI single-beat read transaction.
illustrates a PCI burst read transaction.
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
SYSCLK
SYSCLK
PCI_AD
PCI_AD
PCI Write Transactions
Figure 17-49. PCI Single-Beat Read Transaction
ADDR
ADDR
CMD
CMD
Figure 17-50. PCI Burst Read Transaction
Byte Enables 1
DATA1
Byte Enables
Byte Enables 2
DATA2
DATA
PCI Bus Interface
17-51