MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 1299

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Freescale Semiconductor
0x4_1750–
0x5_0180–
0x4_FFFF
0x5_00C0
0x5_00D0
0x5_0000
0x5_0010
0x5_0020
0x5_0030
0x5_0040
0x5_0050
0x5_0060
0x5_0070
0x5_0080
0x5_0090
0x5_00A0
0x5_00B0
0x5_00E0
0x5_00F0
0x5_0100
0x5_0110
0x5_0120
0x5_0130
0x5_0140
0x5_0150
0x5_0160
0x5_0170
0x5_01F0
0x5_0200
0x5_0210
0x5_0220
0x5_0230
0x5_0240
0x5_0250
Offset
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Reserved
EIVPR0—External interrupt 0 (IRQ0) vector/priority register
EIDR0—External interrupt 0 (IRQ0) destination register
EIVPR1—External interrupt 1 (IRQ1) vector/priority register
EIDR1—External interrupt 1 (IRQ1) destination register
EIVPR2—External interrupt 2 (IRQ2) vector/priority register
EIDR2—External interrupt 2 (IRQ2) destination register
EIVPR3—External interrupt 3 (IRQ3) vector/priority register
EIDR3—External interrupt 3 (IRQ3) destination register
EIVPR4—External interrupt 4 (IRQ4) vector/priority register
EIDR4—External interrupt 4 (IRQ4) destination register
EIVPR5—External interrupt 5 (IRQ5) vector/priority register
EIDR5—External interrupt 5 (IRQ5) destination register
EIVPR6—External interrupt 6 (IRQ6) vector/priority register
EIDR6—External interrupt 6 (IRQ6) destination register
EIVPR7—External interrupt 7 (IRQ7) vector/priority register
EIDR7—External interrupt 7 (IRQ7) destination register
EIVPR8—External interrupt 8 (IRQ8) vector/priority register
EIDR8—External interrupt 8 (IRQ8) destination register
EIVPR9—External interrupt 9 (IRQ9) vector/priority register
EIDR9—External interrupt 9 (IRQ9) destination register
EIVPR10—External interrupt 10 (IRQ10) vector/priority
register
EIDR10—External interrupt 10 (IRQ10) destination register
EIVPR11—External interrupt 11 (IRQ11) vector/priority
register
EIDR11—External interrupt 11 (IRQ11) destination register
Reserved
IIVPR0—Internal interrupt 0 vector/priority register
IIDR0—Internal interrupt 0 destination register
IIVPR1—Internal interrupt 1 vector/priority register
IIDR1—Internal interrupt 1 destination register
IIVPR2—Internal interrupt 2 vector/priority register
IIDR2—Internal interrupt 2 destination register
PIC Register Address Map—Interrupt Source Configuration Registers
Table B-1. Memory Map (continued)
Register
Complete List of Configuration, Control, and Status Registers
Access
Mixed
Mixed
Mixed
Mixed
Mixed
Mixed
Mixed
Mixed
Mixed
Mixed
Mixed
Mixed
Mixed
Mixed
Mixed
Mixed
Mixed
Mixed
Mixed
Mixed
Mixed
Mixed
Mixed
Mixed
Mixed
Mixed
Mixed
Mixed
Mixed
Mixed
—
—
0x8000_0000
0x0000_0001
0x8000_0000
0x0000_0001
0x8000_0000
0x0000_0001
0x8000_0000
0x0000_0001
0x8000_0000
0x0000_0001
0x8000_0000
0x0000_0001
0x8000_0000
0x0000_0001
0x8000_0000
0x0000_0001
0x8000_0000
0x0000_0001
0x8000_0000
0x0000_0001
0x8000_0000
0x0000_0001
0x8000_0000
0x0000_0001
0x8080_0000
0x0000_0001
0x8080_0000
0x0000_0001
0x8080_0000
0x0000_0001
Reset
—
—
10.3.7.1/10-39
10.3.7.2/10-40
10.3.7.1/10-39
10.3.7.2/10-40
10.3.7.1/10-39
10.3.7.2/10-40
10.3.7.1/10-39
10.3.7.2/10-40
10.3.7.1/10-39
10.3.7.2/10-40
10.3.7.1/10-39
10.3.7.2/10-40
10.3.7.1/10-39
10.3.7.2/10-40
10.3.7.1/10-39
10.3.7.2/10-40
10.3.7.1/10-39
10.3.7.2/10-40
10.3.7.1/10-39
10.3.7.2/10-40
10.3.7.1/10-39
10.3.7.2/10-40
10.3.7.1/10-39
10.3.7.2/10-40
10.3.7.3/10-41
10.3.7.4/10-42
10.3.7.3/10-41
10.3.7.4/10-42
10.3.7.3/10-41
10.3.7.4/10-42
Section/Page
—
B-33