MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 958

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Offset 0x110
Reset
DMA Controller
Table 16-9
16.3.1.5
The source address registers, shown in
reads data. In direct mode, if MRn[CDSM/SWSM] and MRn[SRW] are set, a write to this register
simultaneously sets MRn[CS], starting a DMA transfer. Software must ensure that this is a valid address.
16-16
12–15
16–27
28–31
8–11
Bits
0–6
W
R
7
0x190
0x210
0x290
0 1
— SBPATMU — STFLOWLVL SPCIORDER SSME STRANSINT SREADTTYPE
SREADTTYPE DMA source transaction type. Reserved values will result in a programming error being detected and
describes the fields of the SATRn.
2
Name
SSME
ESAD
—
—
—
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Source Address Registers (SAR n )
3
Reserved
Source stride mode enable
0 Stride mode disabled
1 Stride mode enabled
Ignored in basic mode (MR n [XFE] is cleared). Striding on the source address can be accomplished
by enabling SATR n [SSME] and setting the desired stride size and distance in the SSR n .
Reserved
logged in SR[PE].
0000–0001 Reserved
0011 Reserved
0100 Read, don’t snoop local processor
0101 Read, snoop local processor
0111 Read, unlock L2 cache line
1000–1111 Reserved
Reserved
Extended source address.
ESAD represents the four high-order bits of the 36-bit source address.
4
Transaction type to run on local address space
Figure 16-9. Source Attributes Registers (SATR n )
5
Table 16-9. SATR n Field Descriptions
6
Figure
16-10, contain the address from which the DMA controller
7
8
All zeros
Description
11 12
15 16
Freescale Semiconductor
—
Access: Read/Write
27 28
ESAD
31