MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 498

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Security Engine (SEC) 2.1
12.3.2.1
Table 12-5
govern the choices for these fields:
12-18
Bits
30
31
1. EU_SEL0 values of no EU selected or reserved result in an unrecognized header error condition
2. The only valid choices for EU_SEL1 are No EU selected or MDEU. Any other choice results in an
3. If EU_SEL1 is MDEU, then EU_SEL0 must be DEU, AESU, or AFEU. All other values of
during processing of the descriptor header.
unrecognized header error condition.
EU_SEL0 result in an unrecognized header error condition.
Name
DIR
DN
shows the values for EU_SEL0 and EU_SEL1 in the descriptor header. The following rules
Selecting Execution Units—EU_SEL0 and EU_SEL1
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Direction. Direction of overall data flow.
0 Outbound
1 Inbound
This, along with the DESC_TYPE field, helps determine the sequence of actions to be performed by the
channel and selected EUs.
Done notification.
0 No done notification.
1 Signal done to the host on completion of this descriptor.
This enables done notification if the NT field is 1 in the channel configuration register (see
The done notification can take the form of an interrupt, a writeback in the DONE field of this header dword
(see
CDWE (channel done writeback enable) bits in the channel configuration register.
Table
Table 12-4. Header Dword Bit Definitions (continued)
12-51), or both, depending upon the states of the CDIE (channel done interrupt enable) and
Table 12-5. EU_SEL0 and EU_SEL1 Values
(binary)
others
Value
0000
0001
0010
0011
0100
0101
0110
0111
1111
No EU selected
AFEU
DEU
MDEU
RNG
PKEU
AESU
KEU
Reserved
Reserved for header writeback
Selected EU
Description
Freescale Semiconductor
Table
12-50).