MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 917

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Table 15-152
Table 15-153
Freescale Semiconductor
Set up the MII Mgmt for a write cycle to the external PHY Auxiliary Control and Status Register to configure the PHY
eTSEC Signals
GTX_CLK125
set source clock divide by 14 for example to insure that MDC clock speed is not greater than 2.5 MHz
MDIO
Assign a Physical address to the TBI so as to not conflict with the external PHY Physical address,
MDC
describes the shared signals of the GMII interface.
describes the register initializations required to configure the eTSEC in GMII mode.
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Sum
Write to MII Mgmt Control with 16-bit data intended for the external PHY register,
through the Management interface (overrides configuration signals of the PHY),
(This example has Full Duplex = 1, Preamble count = 7, PAD/CRC append = 1)
MACSTNADDR2[0110_0000_0000_0010_0000_0000_0000_0000]
MACSTNADDR1[0100_0011_0110_0101_1000_0111_1000_1100]
I/O
I/O
MIIMIND ---> [0000_0000_0000_0000_0000_0000_0000_0000]
O
I
Table 15-153. GMII Mode Register Initialization Steps
MACCFG1[1000_0000_0000_0000_0000_0000_0000_0000]
MACCFG1[0000_0000_0000_0000_0000_0000_0000_0000]
MACCFG2[0000_0000_0000_0000_0111_0010_0000_0101]
MIIMCON[0000_0000_0000_0000_0000_0000_0000_0100]
MIIMCFG[1000_0000_0000_0000_0000_0000_0000_0111]
MIIMCFG[0000_0000_0000_0000_0000_0000_0000_0101]
MIIMADD[0000_0000_0000_0000_0000_0000_0001_1100]
ECNTRL[0000_0000_0000_0000_0001_0000_0000_0000]
Set station address to 02_60_8C_87_65_43, for example.
Set station address to 02_60_8C_87_65_43, for example.
Read MII Mgmt Indicator register and check for Busy = 0,
TBIPA[0000_0000_0000_0000_0000_0000_0000_0101]
Signals
Perform an MII Mgmt write cycle to the external PHY.
No. of
Initialize MACCFG2, for GMII, Full duplex operation.
This indicates that the eTSEC MII Mgmt bus is idle.
1
1
1
Table 15-152. Shared GMII Signals
(This example has Statistics Enable = 1)
Reset the management interface,
Setup the MII Mgmt clock speed,
Initialize MAC Station Address,
Initialize MAC Station Address,
GTX_CLK125
GMII Signals
Set to 05, for example.
MDIO
MDC
Initialize ECNTRL,
Clear Soft_Reset,
Set I/F Mode bit.
Set Soft_Reset,
Sum
I/O
I/O
O
I
Signals
No. of
1
1
1
Enhanced Three-Speed Ethernet Controllers
Management interface clock
Management interface I/O
Reference clock
Function
15-185