MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 1218

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Device Performance Monitor
20-18
Reads or writes from eTSEC 1 or 3
Reads or writes from high speed
interfaces (PCI and PEX2)
Reads or writes from high speed
interfaces (PCI and PCI Express)
Reads or writes from DMA
Reads or writes from Security
Row open table hits for reads or writes
from core
Row open table hits for reads or writes
from eTSEC 1 or 3
Row open table hits for reads or writes
from high speed interfaces (PCI and
PEX2)
Row open table hits for reads or writes
from high speed interfaces (PCI and
PCI Express)
Row open table hits for reads or writes
from DMA
Row open table hits for reads or writes
from Security
MEM TQ read/write address collision
Channel 0 read request
Channel 1 read request
Channel 2 read request
Channel 3 read request
Channel 0 write request
Channel 1 write request
Channel 2 write request
Channel 3 write request
Channel 0 descriptor request
Channel 1 descriptor request
Channel 2 descriptor request
Channel 3 descriptor request
Channel 0 read DW or less
Event Counted
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Table 20-10. Performance Monitor Events (continued)
C1:68 and C5:117 DMA channel 0 read double word valid
Number
Memory Target Queue Events
C5:105
C6:108
C7:105
C8:105
Ref:14
C3:65
C3:66
C4:67
C5:66
C6:69
C6:65
C6:66
C7:65
C8:66
C7:68
C5:69
C1:66
C2:69
C3:68
C4:70
C1:67
C2:70
C3:69
C4:71
DMA Controller Events
—
—
—
—
—
—
—
—
—
—
—
—
DMA channel 0 read request active in the system
DMA channel 1 read request active in the system
DMA channel 2 read request active in the system
DMA channel 3 read request active in the system
DMA channel 0 write request active in the system
DMA channel 1 write request active in the system
DMA channel 2 write request active in the system
DMA channel 3 write request active in the system
DMA channel 0 descriptor request active in the system
DMA channel 1 descriptor request active in the system
DMA channel 2 descriptor request active in the system
DMA channel 3 descriptor request active in the system
Description of Event Counted
Freescale Semiconductor