MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 1336

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Sleep mode, 1-20, 19-29, 19-34
Snooping
Soft reset, 19-18
SPEFSCR (signal processing and embedded floating-point
SPRGn (software-use registers 0–7), see e500 core, registers
SRAM, see L2 cache/SRAM, 7-27
SRESET (soft reset) signal, 4-2, 4-8
SRR0–1 (save/restore registers 0–1), see e500 core, registers
Stashing, see L2 cache/SRAM, stashing, 7-25
SVR (system version register), see e500 core, registers
SYSCLK (system clock input) signal, 4-3
T
TA (LBC data transfer acknowledge) signal, 14-34
Target-disconnect, see PCI/PCI-X controller
TBL (time base lower register), see e500 core, registers
TBU (time base upper register), see e500 core, registers
TCK (JTAG test clock) signal, 21-8
TCR (timer control register), see e500 core, registers
TDI (JTAG test data input) signal, 21-8
TDO (JTAG test data output) signal, 21-9
Termination
Test interface, see JTAG test access port
TEST_SEL (factory test) signal, 21-6
THERM[0:1] (thermal resistor access) signals, 21-9
Timing diagrams
TLB0CFG (TLB0 configuration register), see e500 core,
TLB1CFG (TLB1 configuration register), see e500 core,
TMS (JTAG test mode select) signal, 21-9
Trace buffer
Index-20
watchpoint monitor
see also Global utilities, power management
power management and snooping (global utilities), 19-34
PCI/PCI-X, termination of PCI transactions, 17-52
PCI/PCI-X transactions, 17-50
and watchpoint monitor, block diagram, 21-1
as a second watchpoint monitor, 21-28
functional description, 21-28–21-30
initialization, 21-31
modes of triggering and arming, 21-4
overview, 21-1
register descriptions, 21-16–21-23
see also Watchpoint monitor, 21-4
HRESET_REQ (hard reset request), 4-2, 11-18, 11-19
READY, 4-2, 21-24, 21-25
SRESET (soft reset), 4-2, 4-8
TRIG_IN (watchpoint trigger in), 21-8, 21-12, 21-18
TRIG_OUT (watchpoint trigger out), 21-8, 21-24
status and control register), see e500 core, registers
registers
registers
by acronym, see Register Index
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Transactions
TRIG_IN (watchpoint trigger in) signal, 21-8, 21-12, 21-18
TRIG_OUT (watchpoint trigger out) signal, 21-8, 21-24
TRST (JTAG test reset) signal, 21-9
TSECn_COL (eTSEC 1–4 collision input) signals, 15-9
TSECn_CRS (eTSEC 1–4 carrier sense input/FIFO receiver
TSECn_GTX_CLK (eTSEC 1–4 gigabit transmit clock)
TSECn_RX_CLK (eTSEC 1–4 receive clock) signals, 15-10
TSECn_RX_DV (eTSEC 1–4 receive data valid) signals,
TSECn_RX_ER (eTSEC 1–4 receive error) signals, 15-11
TSECn_RXD[7:0] (eTSEC 1–4 receive data in) signals,
TSECn_TX_CLK (eTSEC 1–4 transmit clock in) signals,
TSECn_TX_EN (eTSEC 1–4 transmit data valid) signals,
TSECn_TX_ER (eTSEC 1–4 transmit error) signals, 15-12
TSECn_TXD[7:0] (eTSEC 1–4 transmit data out) signals,
TSR (timer status register), see e500 core, registers
U
UART_CTS[0:1] (DUART clear to send) signals, 13-1, 13-3
UART_RTS[0:1] (DUART request to send) signals, 13-1,
UART_SIN [0:1] (DUART transmitter serial data in) signals,
UART_SOUT [0:1] (DUART transmitter serial data out)
UDE (unconditional debug event) signal, 10-8
Universal asynchronous receiver/transmitter, see DUART
UPMCn (user performance monitor counter registers 0–3),
UPMGC0 (user performance monitor global control register
UPMLCan (user performance monitor local control registers
UPMLCbn (user performance monitor local control registers
UPWAIT (LBC UPM wait) signal, 14-6, 14-59
USPRG0 (user software-use register 0), see e500 core,
traced data formats relative to TBCR1[IFSEL]
PCI/PCI-X see PCI/PCI-X controller, transactions
DDR trace buffer entry, 21-29
ECM trace buffer entry, 21-28
PCI trace buffer entry, 21-29, 21-30
flow control) signals, 15-9
signals, 15-9
15-10
15-11
15-11
15-12
15-12
13-3, 13-4
13-2, 13-3
signals, 13-2, 13-3
see e500 core, registers
0), see e500 core, registers
a0–a3), see e500 core, registers
b0–b3), see e500 core, registers
registers
Freescale Semiconductor