MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 1270

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Complete List of Configuration, Control, and Status Registers
B-4
0x100–
0x114
0x500
0x500
0x500
0x501
0x501
0x502
0x502
0x502
0x503
0x504
0x505
0x506
0x507
0x510
0x600
0x600
0x600
0x601
0x601
0x602
0x602
0x602
0x603
0x604
0x605
0x606
0x607
Offset
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
I
URBR—ULCR[DLAB] = 0 UART0 receiver buffer register
UTHR—ULCR[DLAB] = 0 UART0 transmitter holding register
UDLB—ULCR[DLAB] = 1 UART0 divisor least significant
byte register
UIER—ULCR[DLAB] = 0 UART0 interrupt enable register
UDMB—ULCR[DLAB] = 1 UART0 divisor most significant
byte register
UIIR—ULCR[DLAB] = 0 UART0 interrupt ID register
UFCR—ULCR[DLAB] = 0 UART0 FIFO control register
UAFR—ULCR[DLAB] = 1 UART0 alternate function register
ULCR—ULCR[DLAB] = x UART0 line control register
UMCR—ULCR[DLAB] = x UART0 modem control register
ULSR—ULCR[DLAB] = x UART0 line status register
UMSR—ULCR[DLAB] = x UART0 modem status register
USCR—ULCR[DLAB] = x UART0 scratch register
UDSR—ULCR[DLAB] = x UART0 DMA status register
URBR—ULCR[DLAB] = 0 UART1 receiver buffer register
UTHR—ULCR[DLAB] = 0 UART1 transmitter holding register
UDLB—ULCR[DLAB] = 1 UART1 divisor least significant
byte register
UIER—ULCR[DLAB] = 0 UART1 interrupt enable register
UDMB_ULCR[DLAB] = 1 UART1 divisor most significant
byte register
UIIR—ULCR[DLAB] = 0 UART1 interrupt ID register
UFCR—ULCR[DLAB] = 0 UART1 FIFO control register
UAFR—ULCR[DLAB] = 1 UART1 alternate function register
ULCR—ULCR[DLAB] = x UART1 line control register
UMCR—ULCR[DLAB] = x UART1 modem control register
ULSR—ULCR[DLAB] = x UART1 line status register
UMSR—ULCR[DLAB] = x UART1 modem status register
USCR—ULCR[DLAB] = x UART1 scratch register
2
C2 Registers
2
Table B-1. Memory Map (continued)
Register
Block Base Address: 0x0_3000
Block Base Address: 0x0_4000
DUART Registers
I
2
C2 Registers
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
W
W
W
W
R
R
R
R
R
R
R
R
R
Reset
0x00
0x00
0x00
0x00
0x00
0x01
0x00
0x00
0x00
0x00
0x60
0x00
0x00
0x01
0x00
0x00
0x00
0x00
0x00
0x01
0x00
0x00
0x00
0x00
0x60
0x00
0x00
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