MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 57

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

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Freescale Semiconductor
Maximum Frame Length Register Definition..................................................................... 15-73
MII Management Configuration Register Definition ......................................................... 15-73
MIIMCOM Register Definition .......................................................................................... 15-74
MIIMADD Register Definition .......................................................................................... 15-75
MII Mgmt Control Register Definition............................................................................... 15-75
MIIMSTAT Register Definition .......................................................................................... 15-76
MII Mgmt Indicator Register Definition ............................................................................ 15-76
Interface Status Register Definition .................................................................................... 15-77
MAC Station Address Part 1 Register Definition ............................................................... 15-78
MAC Station Address Part 2 Register Definition ............................................................... 15-78
MAC Exact Match Address n Part 1 Register Definition ................................................... 15-79
MAC Exact Match Address x Part 2 Register Definition ................................................... 15-79
Transmit and Receive 64-Byte Frame Register Definition ................................................. 15-80
Transmit and Receive 65- to 127-Byte Frame Register Definition .................................... 15-81
Transmit and Received 128- to 255-Byte Frame Register Definition ................................ 15-81
Transmit and Received 256- to 511-Byte Frame Register Definition................................. 15-82
Transmit and Received 512- to 1023-Byte Frame Register Definition .............................. 15-82
Transmit and Received 1024- to 1518-Byte Frame Register Definition ............................ 15-83
Transmit and Received 1519- to 1522-Byte VLAN Frame Register Definition ................ 15-83
Receive Byte Counter Register Definition.......................................................................... 15-84
Receive Packet Counter Register Definition ...................................................................... 15-84
Receive FCS Error Counter Register Definition................................................................. 15-85
Receive Multicast Packet Counter Register Definition ...................................................... 15-85
Receive Broadcast Packet Counter Register Definition ..................................................... 15-86
Receive Control Frame Packet Counter Register Definition .............................................. 15-86
Receive Pause Frame Packet Counter Register Definition ................................................. 15-87
Receive Unknown OPCode Packet Counter Register Definition ....................................... 15-87
Receive Alignment Error Counter Register Definition....................................................... 15-88
Receive Frame Length Error Counter Register Definition ................................................. 15-88
Receive Code Error Counter Register Definition ............................................................... 15-89
Receive Carrier Sense Error Counter Register Definition .................................................. 15-89
Receive Undersize Packet Counter Register Definition ..................................................... 15-90
Receive Oversize Packet Counter Register Definition ....................................................... 15-90
Receive Fragments Counter Register Definition ................................................................ 15-91
Receive Jabber Counter Register Definition....................................................................... 15-91
Receive Dropped Packet Counter Register Definition ....................................................... 15-92
Transmit Byte Counter Register Definition ........................................................................ 15-92
Transmit Packet Counter Register Definition ..................................................................... 15-93
Transmit Multicast Packet Counter Register Definition ..................................................... 15-93
Transmit Broadcast Packet Counter Register Definition .................................................... 15-94
Transmit Pause Control Frame Counter Register Definition .............................................. 15-94
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
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