MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 715

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

To improve the timing margins a PLL is used to generate external clocks, which minimize the skew
between the local bus and the memory clock.
PLL.
14.5.4.4
Contrary to older DRAM technologies, SDRAM devices typically are organized either x4, x8, x16, or x32.
There are no mainstream devices that include parity support. To allow for error protection on the local bus
an additional SDRAM for the 4 parity bits must be used. Since the local bus allows for SDRAM accesses
with less than the full port size, read-modify-write cycles are supported for SDRAM write cycles.
Freescale Semiconductor
LBC output signals on pins
RBC (reference bus clock)
LSYNC_IN
LSYNC_OUT
LCLK
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Parity Support for SDRAM
Figure 14-77. Local Bus PLL Operation
t
D
= t
PLL
Figure 14-77
+t
P
t
P
t
L
shows relative timings for the local bus clock
Local Bus Controller
14-95