MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 612

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

DUART
13.3.1.10
The UMSRs track the status of the modem (or external peripheral device) clear to send (CTS) signal for
the corresponding UART.
Figure 13-12
Table 13-17
13-16
Bits Name
5
6
7
Bits
0–2
4–6
3
7
OE
DR
PE
Offset 0x506
Reset
Name
DCTS Clear to send.
CTS
W
—
—
R
Parity error.
0 This bit is cleared when ULSR is read or when a new character is loaded into the URBR.
1 Unexpected parity value encountered when receiving data. In FIFO mode, the character with the error is at the
Overrun error.
0 This bit is cleared when ULSR is read.
1 Before the URBR is read, the URBR was overwritten with a new character. The old character is loss. In FIFO
Data ready.
0 This bit is cleared when URBR is read or when all of the data in the receiver FIFO is read.
1 A character has been received in the URBR or the receiver FIFO.
0x606
describes the fields of the UMSRs.
shows the bits in the UMSRs.
top of the FIFO.
mode, the receiver FIFO is full (regardless of the receiver FIFO trigger level setting) and a new character has
been received into the internal receiver shift register. The old character was overwritten by the new character.
Data in the receiver FIFO was not overwritten.
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Reserved.
Clear to send. Represents the inverted value of the CTS input pin from the external peripheral device
0 Corresponding CTS n is negated
1 Corresponding CTS n is asserted. The modem or peripheral device is ready for data transfers.
Reserved.
0 No change on the corresponding CTS n signal since the last read of UMSR[CTS]
1 The CTS n value has changed, since the last read of UMSR[CTS]. Causes an interrupt if UIER[EMSI] is set
Modem Status Registers (UMSR0, UMSR1)
to detect this condition
0
Table 13-16. ULSR Field Descriptions (continued)
—
Figure 13-12. Modem Status Register (UMSR)
Table 13-17. UMSR Field Descriptions
2
CTS
3
Description
All zeros
Description
4
—
Freescale Semiconductor
6
Access: Read only
DCTS
7