MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 774

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Enhanced Three-Speed Ethernet Controllers
15-42
8–15
Bits
16
17
18
19
20
21
22
6
7
THLT6 Transmit halt of ring 6. Set by the eTSEC if is no longer processing transmit frames from this TxBD ring, and
THLT7 Transmit halt of ring 7. Set by the eTSEC if is no longer processing transmit frames from this TxBD ring, and
Name
TXF0 Transmit frame event occurred on ring 0. Set by the eTSEC if IEVENT[TXF] was set in relation to transmitting
TXF1 Transmit frame event occurred on ring 1. Set by the eTSEC if IEVENT[TXF] was set in relation to transmitting
TXF2 Transmit frame event occurred on ring 2. Set by the eTSEC if IEVENT[TXF] was set in relation to transmitting
TXF3 Transmit frame event occurred on ring 3. Set by the eTSEC if IEVENT[TXF] was set in relation to transmitting
TXF4 Transmit frame event occurred on ring 4. Set by the eTSEC if IEVENT[TXF] was set in relation to transmitting
TXF5 Transmit frame event occurred on ring 5. Set by the eTSEC if IEVENT[TXF] was set in relation to transmitting
TXF6 Transmit frame event occurred on ring 6. Set by the eTSEC if IEVENT[TXF] was set in relation to transmitting
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MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
DMA from this ring is disabled. To re-start transmission from this TxBD ring, this bit must be cleared by writing
1 to it. This bit is set only on a general error condition (as in IEVENT[TXE]), regardless of TQUEUE[EN6], or
if no ready TxBDs can be fetched. DMACTRL[GTS] being set by the user does not cause this bit to be set.
Software should examine the halted queue's buffer descriptors for repeatable error conditions before taking it
out of the halt state. Failure to do so may cause an effective livelock, in which the error condition recurs and
halts all queues again.
Repeatable error conditions which cause halt include:
Bus error:
TxBD programming errors:
DMA from this ring is disabled. To re-start transmission from this TxBD ring, this bit must be cleared by writing
1 to it. This bit is set only on a general error condition (as in IEVENT[TXE]), regardless of TQUEUE[EN7], or
if no ready TxBDs can be fetched. DMACTRL[GTS] being set by the user does not cause this bit to be set.
Software should examine the halted queue's buffer descriptors for repeatable error conditions before taking it
out of the halt state. Failure to do so may cause an effective livelock, in which the error condition recurs and
halts all queues again.
Repeatable error conditions which cause halt include:
Bus error:
TxBD programming errors:
Reserved
a frame from this ring.
a frame from this ring.
a frame from this ring.
a frame from this ring.
a frame from this ring.
a frame from this ring.
a frame from this ring.
• Invalid BD or data address
• Uncorrectable error on BD or data read
• Ready=1 and length=0
• Invalid BD or data address
• Uncorrectable error on BD or data read
• Ready=1 and length=0
Table 15-16. TSTAT Field Descriptions (continued)
Description
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