MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 1248
![MPU POWERQUICC III 783-PBGA](/photos/37/62/376266/mpc8544e_image_sml.jpg)
MPC8544VTALF
Manufacturer Part Number
MPC8544VTALF
Description
MPU POWERQUICC III 783-PBGA
Manufacturer
Freescale Semiconductor
Datasheets
1.MPC8544VTALF.pdf
(117 pages)
2.MPC8544VTALF.pdf
(2 pages)
3.MPC8544VTALF.pdf
(1340 pages)
Specifications of MPC8544VTALF
Processor Type
MPC85xx PowerQUICC III 32-Bit
Speed
667MHz
Voltage
1V
Mounting Type
Surface Mount
Package / Case
783-FCPBGA
Processor Series
MPC85xx
Core
e500
Data Bus Width
32 bit
Maximum Clock Frequency
667 MHz
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Data Ram Size
32 KB
I/o Voltage
1.8 V, 3.3 V
Interface Type
I2C, HSSI, DUART
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC8544VTALF
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MPC8544VTALFA
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Debug Features and Watchpoint Facility
Table 21-15
21-18
21–23 STRT Start condition. Specifies the event that arms the trace buffer to start looking for the programmed event
24–28
29–31 STOP Trace stop mode. Specifies the event that stops the updating of the trace buffer after it has been started. Trace
Offset 0x044
Reset
11–15
Bits
8–10
Bits
0–4
5–7
W
R
0
Name
Name
IFSEL Interface selection. Specifies the interface that sources information for both comparison/buffer control and
—
SID
—
—
describes the TBCR1 fields.
—
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
000 No event. Armed immediately
001 Watchpoint monitor event is detected
010 Trace buffer event is detected
011 Performance monitor signals overflow
100 TRIG_IN transitions from 0 to 1
101 TRIG_IN transitions from 1 to 0
110 Current context ID equals programmed context ID
111 Current context ID does not equal programed context ID
Reserved
buffer only stops after it has been triggered at least once.
000 Buffer is full
001 Watchpoint monitor event is detected
010 Trace buffer event is detected
011 Performance monitor signals overflow
100 TRIG_IN transitions from 0 to 1
101 TRIG_IN transitions from 1 to 0
110 Current context ID equals programmed context ID
111 Current context ID does not equal programed context ID
Reserved
buffer data capture.
000 Selects e500 coherency module (ECM) dispatch interface
001 Selects internal DDR SDRAM interface
010 Selects internal PCI outbound interface
011 Reserved
100 Selects internal PCI Express 1 outbound interface
101 Selects internal PCI Express 2 outbound interface
110 Selects internal PCI Express 3 outbound interface
111 Reserved
Reserved
Source ID. Specifies the source ID associated with TBCR0[SIDEN]. The source ID is defined in
4
5
IFSEL
Figure 21-9. Trace Buffer Control Register 1 (TBCR1)
Table 21-14. TBCR0 Field Descriptions (continued)
7
8
Table 21-15. TBCR1 Field Descriptions
—
10
11
SID
All zeros
Description
Description
15 16
—
Freescale Semiconductor
26 27
Access: Read/Write
Table
TID
21-26.
31
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