MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 1125

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

18.3.9.7
The PCI Express device capabilities register is shown in
18.3.9.8
The PCI Express device control register is shown in
Freescale Semiconductor
Offset 0x54
Reset
Offset 0x50
Reset
Reset
31–28
27–26
25–18
17–15
11–9
Bits
8–6
4–3
2–0
W
14
13
12
R
5
W
W
R
R
15
—
0
—
31
15
0
0
MAX_PL_SIZE_SUP
MAX_READ_SIZE
PCI Express Device Capabilities Register—0x50
PCI Express Device Control Register—0x54
14
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
EP_L0s_LAT
0
PIP
EP_L1_LAT
PHAN_FCT
14
0
0
CSPLS
CSPLV
Name
Table 18-80. PCI Express Device Capabilities Register Field Description
ABP
PIP
AIP
—
ET
—
—
1
AIP
13
0
0
Figure 18-85. PCI Express Device Capabilities Register
12
0
ABP
28
12
0
0
Figure 18-86. PCI Express Device Control Register
Reserved
Captured Slot Power Limit Scale
Captured Slot Power Limit Value
Reserved
Power Indicator Present
Attention Indicator Present
Attention Button Present
Endpoint L1 Acceptable Latency
Endpoint L0s Acceptable Latency
Extended Tag Field Supported
Phantom Functions Supported
Maximum payload size supported. 001 = 256-bytes
NSE
11
1
27
11
0
0
CSPLS
EP_L1_LAT
APE
10
0
26
0
0
PFE
0
9
25
1
9
0
ETE
0
8
1
0
8
Figure
EP_L0s_LAT
MAX_PAYLOAD_SIZE
Figure
0
7
1
0
18-86.
Description
1
0
6
18-85.
CSPLV
0
ET
1
0
5
5
0
PHAN_FCT
1
0
4
RO
1
4
PCI Express Interface Controller
1
0
3
URR
0
3
MAX_PL_SIZE_SUP
18
1
0
2
Access: Read-only
FER NFER CER
Access: Read/write
0
2
17
0
0
0
1
—
18-71
16
0
1
0
0
0