MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 196

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Core Complex Overview
5.3.1
The e500v2 provides the following additional features not supported by the e500v1:
Detailed descriptions of these differences are provided in their respective chapters.
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— Power-saving modes: core-halted and core-stopped
— Internal clock multipliers ranging from 1 to 8 times the bus clock, including integer and
— Dynamic power management of execution units, caches, and MMUs
— NAP, DOZE, and SLEEP bits in HID0 can be used to assert nap, doze, and sleep output signals
Testability
— LSSD scan design
— JTAG interface
— ESP support
Reliability and serviceability
— Parity checking on caches
— Parity checking on e500 local bus
The e500v2 uses 36-bit physical addressing, which is supported by the following:
— MMU assist register 7 (MAS7)
— HID0[EN_MAS7_UPDATE]
— Programmable jumper options to specify the upper bits of the reset vector.
The e500v2 has a 512-entry, 4-way set-associative unified TLB for TLB1.
The maximum variable page size is extended to 4 Gbytes.
Embedded double-precision floating-point support has been added. These instructions use the
64-bit GPRs as single, 64-bit double-precision operands. This functionality is enabled through
MSR[SPE].
Slightly different functionality of HID1[RFXE] bit.
The data line fill buffer in the LSU is expanded from three to five entries.
The load miss queue in the LSU is expanded from four to nine entries.
TBSEL and TBEE bits have been added to the performance monitor global control register 0
(PMGC0) to support monitoring of time base events.
Minor modifications to the SPE instruction set.
Data cache flush assist capability, supported through HID0[DCFA]. When DCFA is set, the cache
miss replacement algorithm ignores invalid entries and follows the replacement sequence defined
by the PLRU bits. This reduces the series of uniquely addressed load or dcbz instructions required
to flush the cache.
half-mode multipliers.
to initiate power-saving modes at the integrated device level.
e500v2 Differences
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Freescale Semiconductor