MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 549

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

12.4.6.2
The AESU key size register stores the number of bytes in the key (16,24,32). Any key data beyond the
number of bytes in the key size register will be ignored. This register is cleared when the AESU is reset or
re-initialized. If a key size other than 16, 24, or 32 bytes is specified, an illegal key size error is generated.
If the key size register is modified during processing, a context error is generated.
12.4.6.3
The AESU data size register, shown in
Acceptable sizes vary depending on the AES mode selected. In ECB, CBC, and CTR mode, the message
processed by the AESU must be a multiple of 128 bits; the AESU does not automatically pad messages
out to 128-bit blocks. In CCM mode, data size must be a multiple of 8 bits. In XOR mode the data size
Freescale Semiconductor
Address AESU 0x3_4008
Reset
W
R
0
AESU Key Size Register (AESUKSR)
AESU Data Size Register (AESUDSR)
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Note on restore decrypt key (RDK)—In most networking applications, the
decryption of an AES protected packet is performed as a single operation.
However, if circumstances dictate that the decryption of a message should
be split across multiple descriptors, the AESU allows the user to save the
decrypt key, and the active AES context, to memory for later re-use. This
saves the internal AESU processing overhead associated with regenerating
the decryption key schedule (~12 AESU clock cycles for the first block of
data to be decrypted.)
The use of RDK is completely optional, as the input time of the preserved
decrypt key may exceed the ~12 cycles required to restore the decrypt key
for processing the first block.
To use RDK, the following procedure is recommended:
The descriptor type used in decryption of the first portion of the message is
0100_0- AESU key expand output. The AESU mode must be decrypted.
See
write the contents of the context registers and the key registers (containing
the expanded decrypt key) to memory.
To process the remainder of the message, use a common descriptor type
(0001_0), and set the restore decrypt key mode bit. Load the context
registers and the expanded decrypt key with previously saved key and
context data from the first message. The key size is written as before (16,
24, or 32 bytes).
Table 12-6
for more information. The descriptor causes the SEC to
Figure 12-48. AESU Key Size Register
Figure
—
12-49, stores the number of bits in the final message block.
NOTE
All zeros
51 52
Security Engine (SEC) 2.1
Access: Read/write
Key Size
12-69
63