MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 801

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

15.5.3.5.2
The MACCFG2 register is written by the user.
register.
Table 15-40
Freescale Semiconductor
Offset eTSEC1:0x2_4504; eTSEC3:0x2_5504
Reset
Reset 0 1 1 1 0 0
16–19
20–21
22–23
0–15
Bits
Bits
30
31
24
W
W
R
R Preamble
16
0
Length
Sync’d Tx EN Transmit enable synchronized to the transmit stream. (Read-only)
PreAM RxEN User defined preamble enable for received frames. This bit is cleared by default.
Preamble
I/F Mode
Tx_EN
Length
Name
Name
describes the fields of the MACCFG2 register.
19 20 21
—
—
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
MAC Configuration 2 Register (MACCFG2)
—
0 Frame transmission is not enabled.
1 Frame transmission is enabled.
Transmit enable. This bit is cleared by default. If set, prior to clearing this bit, set DMACTRL[GTS] then
confirm subsequent occurrence of the graceful receive stop interrupt (IEVENT[GTSC] is set).
0 The MAC may not transmit frames from the system.
1 The MAC may transmit frames from the system.
Reserved
This field determines the length in bytes of the preamble field preceding each Ethernet start-of-frame
delimiter byte. Values from 0x3 to 0xF are supported by the controller. The default value of 0x7 should
not be altered in order to guarantee reliable operation with IEEE 802.3 compliant hardware.
Reserved
This field determines the type of interface to which the MAC is connected. Its default is 00.
00 Reserved bit mode (not supported) (10 Mbps GENDEC/GPSI)
01 Nibble mode (MII) (10/100 Mbps MII/RMII)
10 Byte mode (GMII/TBI) (1000 Mbps GMII/TBI). Reserved if neither GMII or TBI are supported.
11 Reserved
0 The MAC skips the Ethernet preamble without returning it.
1 The MAC recovers the received Ethernet preamble and passes it to the driver at the start of each
22
Mode
0
I/F
received frame. Not applicable to FIFO or RMII 10/100 modes.
Table 15-39. MACCFG1 Field Descriptions (continued)
23
0
PreAmRxEN PreAmTxEN
Figure 15-37. MACCFG2 Register Definition
Table 15-40. MACCFG2 Field Descriptions
24
0
25
0
Figure 15-37
All zeros
Frame
Huge
—
26
0
Description
Description
describes the definition for the MACCFG2
Length
check
27
0
Enhanced Three-Speed Ethernet Controllers
MPEN
28
0
PAD/CRC CRC EN
29
0
Access: Read/Write
30
0
Duplex
Full
15
31
0
15-69