MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 421
![MPU POWERQUICC III 783-PBGA](/photos/37/62/376266/mpc8544e_image_sml.jpg)
MPC8544VTALF
Manufacturer Part Number
MPC8544VTALF
Description
MPU POWERQUICC III 783-PBGA
Manufacturer
Freescale Semiconductor
Datasheets
1.MPC8544VTALF.pdf
(117 pages)
2.MPC8544VTALF.pdf
(2 pages)
3.MPC8544VTALF.pdf
(1340 pages)
Specifications of MPC8544VTALF
Processor Type
MPC85xx PowerQUICC III 32-Bit
Speed
667MHz
Voltage
1V
Mounting Type
Surface Mount
Package / Case
783-FCPBGA
Processor Series
MPC85xx
Core
e500
Data Bus Width
32 bit
Maximum Clock Frequency
667 MHz
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Data Ram Size
32 KB
I/o Voltage
1.8 V, 3.3 V
Interface Type
I2C, HSSI, DUART
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC8544VTALF
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MPC8544VTALFA
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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10.3.1.8
The spurious vector register (SVR), shown in
processor when the IACK register is read for a spurious interrupt.
Table 10-14
10.3.2
This section describes the global timer registers. Note that each timer has four individual configuration
registers (GTCCRn, GTBCRn, GTVPRn, GTDRn), but they are only shown once in this section.
10.3.2.1
The timer frequency reporting register (TFRR), shown in
clocking frequency of the PIC timers. Note that although TFRR is read/write, the value of this register is
ignored by the PIC unit.
Freescale Semiconductor
16–31 VECTOR Spurious interrupt vector. Value returned when the interrupt acknowledge (IACK) register is read during a
0–15
Offset 0x4_10E0
Offset 0x4_10F0
Reset 0
Bits
Reset
W
W
R
R
0
0
Name
—
0
describes the SVR fields.
Global Timer Registers
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
0
Spurious Vector Register (SVR)
Timer Frequency Reporting Register (TFRR)
Reserved
spurious vector fetch. See
events and conditions that may cause a spurious vector fetch.
0
0
0
Figure 10-11. Timer Frequency Reporting Register (TFRR)
0
0
Figure 10-10. Spurious Vector Register (SVR)
—
0
Table 10-14. SVR Field Descriptions
0
0
Section 10.4.3, “Spurious Vector Generation,”
0
0
Figure
0
0
All zeros
10-10, contains the 16-bit vector returned to the
FREQ
15 16
0
Description
Figure
1
1
1
10-11, is written by software to report the
1
1
1
1
VECTOR
for more information about the
Programmable Interrupt Controller
1
1
1
1
Access: Read/Write
Access: Read/Write
1
1
1
1
10-23
31
31
1
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