MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 1079

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

18.3.5.2.2
In RC mode, the PEXIWBAR[1–3] registers reside outside of the type 1 header; PEXIWBAR0 is the only
inbound BAR that resides in the Type 1 header (at offset 0x10).
If the transaction hits any window, the translation is performed and then the transaction is sent to memory.
If there is no hit to any one of the BARs, then a UR completion will be returned for non-posted
transactions. All posted transactions with no BAR hit are ignored.
Figure 18-19
18.3.5.2.3
The PCI Express inbound translation address registers, shown in
internal platform address to be used. Note that PEXITAR0 does not exist in the memory-mapped space; it
is a fixed 1-Mbyte translation to the internal configuration (CCSRBAR) space.
Freescale Semiconductor
Offset Window 1: 0xDE0
Reset
W
R
Window 2: 0xDC0
Window 3: 0xDA0
0
To Memory
shows the inbound transaction flow in RC mode.
Figure 18-20. PCI Express Inbound Translation Address Registers (PEXITAR n )
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
RC Inbound ATMU Implementation
PCI Express Inbound Translation Address Registers (PEXITAR n )
—
Inbound ATMUs
7
Figure 18-19. RC Inbound Transaction Flow
8
TEA
11 12
Memory or IO Base
Memory or IO Limit
Memory Base
Primary Side
Memory Limit
Prefetchable
Prefetchable
All zeros
Figure
18-20, contain the translated
TA
PCI Express Interface Controller
Secondary Side
Access: Read/Write
18-25
31