MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 1244

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Debug Features and Watchpoint Facility
21.3.1.3
The watchpoint monitor address mask register (WMAMR) shown in
address in the WMAR.
Table 21-10
21.3.1.4
The watchpoint monitor transaction mask register (WMTMR), shown in
transaction types to monitor. WMTMR allows users to qualify watchpoint events specifically with any
combination of transaction types. As shown in
transaction types; one for each interface. Setting a bit enables watchpoint monitoring for the corresponding
transaction types.
Because the supported transaction types vary by interface, the type designated by a WMTMR field also
depends on the interface specified by WMCR1[IFSEL].
each WMTMR bit by interface.
Table 21-11
21-14
Offset 0x014
Reset
Offset 0x018
Reset
0–31
0–31
Bits
Bits
W
W
R
R
0
0
WMAM Watchpoint monitor address mask. A value of zero masks the address comparison for the corresponding
WMTM Watchpoint monitor transaction mask. Each bit corresponds to a transaction type as defined in
Name
Name
describes the WMTMR fields.
describes the WMAMR fields.
Watchpoint Monitor Transaction Mask Register (WMTMR)
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Watchpoint Monitor Address Mask Register (WMAMR)
address bit. These bits only mask the address bits generated by the hardware, but do not affect the bits
specified in WMAR. A bit that is masked from the comparison should be set to 0 in WMAR.
The transaction associated with any particular bit may be different depending on the interface being
monitored. A value of 1 for a given mask bit enables the matching of the transaction associated with that
bit. These bits are meaningful only when WMCR0[TMD]=0.
Figure 21-6. Watchpoint Monitor Transaction Mask Register (WMTMR)
Figure 21-5. Watchpoint Monitor Address Mask Register (WMAMR)
Table 21-10. WMAMR Field Descriptions
Table 21-11. WMTMR Field Descriptions
Table
All zeros
All zeros
WMAM
WMTM
21-11, each bit represents as many as four separate
Table 21-12
Description
Description
Figure 21-5
lists transaction types associated with
Figure
contains the mask for the
21-6, specifies which
Freescale Semiconductor
Access: Read/Write
Access: Read/Write
Table
21-12.
31
31