MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 1275

MPU POWERQUICC III 783-PBGA

MPC8544VTALF

Manufacturer Part Number
MPC8544VTALF
Description
MPU POWERQUICC III 783-PBGA
Manufacturer
Freescale Semiconductor
Datasheets

Specifications of MPC8544VTALF

Processor Type
MPC85xx PowerQUICC III 32-Bit
Speed
667MHz
Voltage
1V
Mounting Type
Surface Mount
Package / Case
783-FCPBGA
Processor Series
MPC85xx
Core
e500
Data Bus Width
32 bit
Maximum Clock Frequency
667 MHz
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Data Ram Size
32 KB
I/o Voltage
1.8 V, 3.3 V
Interface Type
I2C, HSSI, DUART
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MPC8544VTALF
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MPC8544VTALFA
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Freescale Semiconductor
0xC08–
0xC14–
0xC34–
0x018–
0x030–
0xBFC
0xC0C
0xC1C
0xC2C
0xC3C
0x01C
0x02C
0xBF4
0xBF8
0xC00
0xC04
0xC10
0xC20
0xC24
0xC28
0xC30
0x020
0x024
0x028
Offset
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Reserved
PEX_PME_MES_DR—PCI Express PME & message detect
register
PEX_PME_MES_DISR—PCI Express PME & message
disable register
PEX_PME_MES_IER—PCI Express PME & message
interrupt enable register
PEX_PMCR—PCI Express power management command
register
Reserved
IP block revision register 1 (PEX_IP_BLK_REV1)
IP block revision register 2 (PEX_IP_BLK_REV2)
PEXOTAR0—PCI Express outbound translation address
register 0 (default)
PEXOTEAR0—PCI Express outbound translation extended
address register 0 (default)
Reserved
PEXOWAR0—PCI Express outbound window attributes
register 0 (default)
Reserved
PEXOTAR1—PCI Express outbound translation address
register 1
PEXOTEAR1—PCI Express outbound translation extended
address register 1
PEXOWBAR1—PCI Express outbound window base
address register 1
Reserved
PEXOWAR1—PCI Express outbound window attributes
register 1
Reserved
PCI Express Power Management Event & Message Registers
PCI Express IP Block Revision Registers
Table B-1. Memory Map (continued)
Register
Outbound Window 0 (default)
PCI Express ATMU Registers
Outbound Window 1
Complete List of Configuration, Control, and Status Registers
Access
Mixed
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
w1c
R
R
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0208_0100
0x0000_0000
0x0000_0000
0x0000_0000
0x8004_4023
0x0000_0000
0x0000_0000
0x0000_0000
0x0004_4023
Reset
18.3.5.1.1/18-20
18.3.5.1.2/18-21
18.3.5.1.4/18-22
18.3.5.1.1/18-20
18.3.5.1.2/18-21
18.3.5.1.3/18-21
18.3.5.1.4/18-22
18.3.3.1/18-13
18.3.3.2/18-14
18.3.3.3/18-16
18.3.3.4/18-17
18.3.4.1/18-18
18.3.4.2/18-19
Section/Page
B-9

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